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Citations to my articles
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Title / AuthorCited by Year
Dynamic thermal management in 3D multicore architectures
AK Coskun, JL Ayala, D Atienza, TS Rosing, Y Leblebici
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE'09 ...
Power-aware compilation for register file energy reduction
JL Ayala, A Veidenbaum, M López-Vallejo
International Journal of Parallel Programming 31 (6), 451-467
Modeling and dynamic management of 3D multicore systems with liquid cooling
AK Coskun, JL Ayala, D Atienza, TS Rosing
Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International ...
Reliability-aware design for nanometer-scale devices
D Atienza, G De Micheli, L Benini, JL Ayala, PG Del Valle, M DeBole, ...
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific, 549-554
Design of a pipelined hardware architecture for real-time neural network computations
JL Ayala, AG Lomeña, M López-Vallejo, A Fernández
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on ...
Through Silicon Via-based Grid for Thermal Control in 3D Chips
JL Ayala, A Sridhar, D Atienza, Y Leblebici
Design Technology for Heterogeneous Embedded Systems, 303-320
A nanowatt smart temperature sensor for dynamic thermal management
P Ituero, JL Ayala, M Lopez-Vallejo
Sensors Journal, IEEE 8 (12), 2036-2043
Thermal modeling and analysis of 3D multi-processor chips
JL Ayala, A Sridhar, D Cuesta
Integration, the VLSI Journal 43 (4), 327-341
Energy aware register file implementation through instruction predecode
JL Ayala, M López-Vallejo, A Veidenbaum, CA López
Application-Specific Systems, Architectures, and Processors, 2003 ...
Adaptive task migration policies for thermal control in mpsocs
D Cuesta, J Ayala, J Hidalgo, D Atienza, A Acquaviva, E Macii
VLSI 2010 Annual Symposium, 83-115
Leakage-based on-chip thermal sensor for CMOS technology
P Ituero, JL Ayala, M Lopez-Vallejo
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on ...
Energy-efficient register renaming in high-performance processors
JL Ayala, M López-Vallejo, A Veidenbaum
Proceedings of WASP, 56-61
Reducing register file energy consumption using compiler support
JL Ayala, A Veidenbaum
Workshop on Application Specific Processors
Thermal-aware floorplanning exploration for 3D multi-core architectures
D Cuesta, J Ayala, J Hidalgo, M Poncino, A Acquaviva, E Macii
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 99-102
Improving register file banking with a power-aware unroller
JL Ayala, M López-Vallejo
Proceedings of PARC, 15-20
Energy-aware compilation and hardware design for VLIW embedded systems
JL Ayala, M López-Vallejo, D Atienza, P Raghavan, F Catthoor, D Verkest
International Journal of Embedded Systems 3 (1), 73-82
3D Thermal-aware floorplanner for many-core single-chip systems
D Cuesta, JL Risco-Martin, JL Ayala, D Atienza
Test Workshop (LATW), 2011 12th Latin American, 1-6
Thermal-aware compilation for system-on-chip processing architectures
MM Sabry, JL Ayala, D Atienza
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 221-226
A compiler-assisted banked register file architecture
JL Ayala, M López-Vallejo, A Veidenbaum
Workshop on Application Specific Processors
A banked precomputation-based CAM architecture for low-power storage-demanding Applications
P Echeverría, JL Ayala, M López-Vallejo
Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean, 57-60
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