Arjuna Madanayake
Arjuna Madanayake
Associate Professor of Electrical and Computer Engineering at the University of Akron
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Wireless communications and applications above 100 GHz: Opportunities and challenges for 6G and beyond
TS Rappaport, Y Xing, O Kanhere, S Ju, A Madanayake, S Mandal, ...
IEEE Access 7, 78729-78757, 2019
2142019
Improved 8-point approximate DCT for image and video compression requiring only 14 additions
US Potluri, A Madanayake, RJ Cintra, FM Bayer, S Kulasekera, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (6), 1727-1740, 2014
1252014
Deep learning-based automated modulation classification for cognitive radio
GJ Mendis, J Wei, A Madanayake
2016 IEEE International Conference on Communication Systems (ICCS), 1-6, 2016
802016
A speed-optimized systolic array processor architecture for spatio-temporal 2-D IIR broadband beam filters
HLPA Madanayake, LT Bruton
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (7), 1953-1966, 2008
632008
Low-Power VLSI Architectures for DCT\/DWT: Precision vs Approximation for HD Video, Biomedical, and Smart Antenna Applications
A Madanayake, RJ Cintra, V Dimitrov, F Bayer, KA Wahid, S Kulasekera, ...
IEEE Circuits and Systems Magazine 15 (1), 25-47, 2015
492015
Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing
US Potluri, A Madanayake, RJ Cintra, FM Bayer, N Rajapaksha
Measurement Science and Technology 23 (11), 114003, 2012
492012
RF analog beamforming fan filters using CMOS all-pass time delay approximations
C Wijenayake, Y Xu, A Madanayake, L Belostotski, LT Bruton
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (5), 1061-1073, 2012
452012
A Row-Parallel 88 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation
A Madanayake, RJ Cintra, D Onen, VS Dimitrov, N Rajapaksha, LT Bruton, ...
IEEE transactions on circuits and systems for video technology 22 (6), 915-929, 2011
432011
Deep learning based doppler radar for micro UAS detection and classification
GJ Mendis, T Randeny, J Wei, A Madanayake
MILCOM 2016-2016 IEEE Military Communications Conference, 924-929, 2016
412016
A new second-order all-pass filter in 130-nm CMOS
P Ahmadi, B Maundy, AS Elwakil, L Belostotski, A Madanayake
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (3), 249-253, 2015
402015
2D space–time wave-digital multi-fan filter banks for signals consisting of multiple plane waves
N Rajapaksha, A Madanayake, LT Bruton
Multidimensional Systems and Signal Processing 25 (1), 17-39, 2014
402014
A digital hardware fast algorithm and FPGA-based prototype for a novel 16-point approximate DCT for image compression applications
FM Bayer, RJ Cintra, A Edirisuriya, A Madanayake
Measurement Science and Technology 23 (11), 114010, 2012
402012
Multidimensional (MD) circuits and systems for emerging applications including cognitive radio, radio astronomy, robot vision and imaging
A Madanayake, C Wijenayake, DG Dansereau, TK Gunaratne, LT Bruton, ...
IEEE Circuits and Systems Magazine 13 (1), 10-43, 2013
392013
UWB beamforming using 2-D beam digital filters
SV Hum, H Madanayake, LT Bruton
IEEE Transactions on Antennas and Propagation 57 (3), 804-807, 2009
362009
Broadband multiple cone-beam 3-D IIR digital filters applied to planar dense aperture arrays
C Wijenayake, A Madanayake, L Bruton
IEEE Transactions on Antennas and Propagation 60 (11), 5136-5146, 2012
332012
A systolic array 2-D IIR broadband RF beamformer
HLPA Madanayake, SV Hum, LT Bruton
IEEE Transactions on Circuits and Systems II: Express Briefs 55 (12), 1244-1248, 2008
302008
Algebraic integer based 8× 8 2-D DCT architecture for digital video processing
HLPA Madanayake, RJ Cintra, D Onen, VS Dimitrov, LT Bruton
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1247-1250, 2011
292011
Low-noise amplifier design considerations for use in antenna arrays
L Belostotski, B Veidt, KF Warnick, A Madanayake
IEEE Transactions on Antennas and Propagation 63 (6), 2508-2520, 2015
282015
A multiplication-free digital architecture for 16× 16 2-D DCT/DST transform for HEVC
A Edirisuriya, A Madanayake, RJ Cintra, FM Bayer
2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 1-5, 2012
272012
FPGA architectures for real-time 2D/3D FIR/IIR plane wave filters
A Madanayake, L Bruton, C Comis
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
272004
El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.
Artículos 1–20