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Javier Mora
Javier Mora
Electronic engineer, PhD at Universidad Politécnica de Madrid
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Self-reconfigurable evolvable hardware system for adaptive image processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
IEEE Transactions on Computers 62 (8), 1481-1493, 2013
712013
Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems
R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo
2011 International Conference on Reconfigurable Computing and FPGAs, 164-169, 2011
602011
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado
R Zamacola, AG Martínez, J Mora, A Otero, E de La Torre
2018 International Conference on ReConFigurable Computing and FPGAs …, 2018
312018
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems
A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 336-343, 2011
272011
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 184-191, 2011
222011
A novel FPGA-based evolvable hardware system based on multiple processing arrays
A Gallego, J Mora, A Otero, R Salvador, E de la Torre, T Riesgo
Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW …, 2013
192013
Implementation techniques for evolvable HW systems: Virtual vs. dynamic reconfiguration
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
2012 22nd International Conference on Field Programmable Logic and …, 2012
172012
A scalable evolvable hardware processing array
A Gallego, J Mora, A Otero, E de la Torre, T Riesgo
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference …, 2013
162013
Accelerating the evolution of a systolic array-based evolvable hardware system
J Mora, E de la Torre
Microprocessors and Microsystems 56, 144-156, 2018
152018
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
J Mora, A Otero, E de la Torre, T Riesgo
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
142015
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
J Mora, R Salvador, E de la Torre
Genetic Programming and Evolvable Machines 20 (2), 155-186, 2019
92019
A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time
J Valverde Alcalá, A Rodríguez Medina, J Mora de Sambricio, ...
Industriales, 2014
52014
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform
J Mora, Á Gallego, A Otero, E de la Torre, T Riesgo
2013 Conference on Design and Architectures for Signal and Image Processing …, 2013
52013
A noise-agnostic self-adaptive image processing application based on evolvable hardware
J Mora, Á Gallego, A Otero, B López, E de la Torre, T Riesgo
2013 Conference on Design and Architectures for Signal and Image Processing …, 2013
52013
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
R Zamacola, AG Martínez, J Mora, A Otero, E de la Torre
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
42019
A self-adaptive image processing application based on evolvable and scalable hardware
Á Gallego, J Mora, A Otero, B López, E de la Torre, T Riesgo
2013 23rd International Conference on Field programmable Logic and …, 2013
42013
Prospection of Reconfiguration Capabilities using Space Qualified SRAM-based FPGAs for a Satellite Communications Application
F Veljković, J Mora, T Riesgo, E de la Torre, LB Valero, RR Sánchez, ...
31st AIAA International Communications Satellite Systems Conference, 5683, 2013
32013
2D Reconfigurable Systolic Core Architecture for Evolvable Systems
A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina
Proceedings of the XXVI Conference on Design of Circuits and Integrated …, 2011
32011
Evolvable hardware FPGA-based platform for autonomous fault-tolerant systems
J Mora, A Otero, Á Gallego, R Salvador, E de la Torre, T Riesgo, ...
2012 International Conference on ReConFigurable Computing and FPGAs …, 2012
22012
Development of Brain-Computer Interfaces using Evolvable Hardware
B López, J Mora, P Mansanet, E Torre Arnanz, T Riesgo Alcaide
IEEE, 2014
12014
El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.
Artículos 1–20