| SESC simulator J Renau http://sesc. sourceforge. net/, 2005 | 630* | 2005 |
| POSH: a TLS compiler that exploits program structure W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006 | 330 | 2006 |
| Cherry: Checkpointed early resource recycling in out-of-order microprocessors JF Martínez, J Renau, MC Huang, M Prvulovic 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 306 | 2002 |
| Positional adaptation of processors: application to energy reduction MC Huang, J Renau, J Torrellas ACM SIGARCH Computer Architecture News 31 (2), 157-168, 2003 | 263 | 2003 |
| A framework for dynamic energy efficiency and temperature management M Huang, J Renau, SM Yoo, J Torrellas Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000 | 228 | 2000 |
| ESESC: A fast multicore simulator using time-based sampling EK Ardestani, J Renau 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 171 | 2013 |
| Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation J Renau, J Tuck, W Liu, L Ceze, K Strauss, J Torrellas Proceedings of the 19th Annual International conference on Supercomputing …, 2005 | 127 | 2005 |
| L1 data cache decomposition for energy efficiency M Huang, J Renau, SM Yoo, J Torrellas Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 110 | 2001 |
| Power model validation through thermal measurements FJ Mesa-Martinez, J Nayfach-Battilana, J Renau Proceedings of the 34th Annual International Symposium on Computer …, 2007 | 103 | 2007 |
| Characterizing processor thermal behavior FJ Mesa-Martinez, EK Ardestani, J Renau ACM SIGARCH Computer Architecture News 38 (1), 193-204, 2010 | 101 | 2010 |
| Power blurring: Fast static and transient thermal analysis method for packaged integrated circuits and power devices A Ziabari, JH Park, EK Ardestani, J Renau, SM Kang, A Shakouri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (11 …, 2014 | 75 | 2014 |
| Energy-efficient hybrid wakeup logic M Huang, J Renau, J Torrellas Proceedings of the 2002 International Symposium on Low Power Electronics and …, 2002 | 68 | 2002 |
| Programming the FlexRAM parallel intelligent memory system BB Fraguela, J Renau, P Feautrier, D Padua, J Torrellas ACM Sigplan Notices 38 (10), 49-60, 2003 | 62 | 2003 |
| Thread-level speculation on a CMP can be energy efficient J Renau, K Strauss, L Ceze, W Liu, S Sarangi, J Tuck, J Torrellas Proceedings of the 19th annual international conference on Supercomputing …, 2005 | 58 | 2005 |
| CAVA: Using checkpoint-assisted value prediction to hide L2 misses L Ceze, K Strauss, J Tuck, J Torrellas, J Renau ACM Transactions on Architecture and Code Optimization (TACO) 3 (2), 182-208, 2006 | 55 | 2006 |
| /spl mu/Complexity: estimating processor design effort C Bazeghi, FJ Mesa-Martinez, J Renau 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005 | 46 | 2005 |
| Analysis of PARSEC workload scalability G Southern, J Renau 2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016 | 45 | 2016 |
| Rerack: Power simulation for data centers with renewable energy generation M Brown, J Renau ACM SIGMETRICS Performance Evaluation Review 39 (3), 77-81, 2011 | 45 | 2011 |
| Energy-efficient thread-level speculation J Renau, K Strauss, L Ceze, W Liu, SR Sarangi, J Tuck, J Torrellas IEEE Micro 26 (1), 80-91, 2006 | 38 | 2006 |
| Measuring performance, power, and temperature from real processors FJ Mesa-Martinez, M Brown, J Nayfach-Battilana, J Renau Proceedings of the 2007 workshop on Experimental computer science, 16-es, 2007 | 36 | 2007 |
