Minas Dasygenis
Minas Dasygenis
University of Western Macedonia, Greece
Verified email at ieee.org - Homepage
Title
Cited by
Cited by
Year
Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications
D Soudris, ND Zervas, A Argyriou, M Dasygenis, K Tatas, CE Goutis, ...
International Workshop on Power and Timing Modeling, Optimization and …, 2000
492000
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck
M Dasygenis, E Brockmeyer, B Durinck, F Catthoor, D Soudris, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (3), 279-291, 2006
422006
Power and performance exploration of embedded systems executing multimedia kernels
M Dasygenis, N Kroupis, K Tatas, A Argyriou, D Soudris, A Thanailakis
IEE Proceedings-Computers and Digital Techniques 149 (4), 164-172, 2002
152002
A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration
M Dasygenis
2014 9th IEEE International Conference on Design & Technology of Integrated …, 2014
112014
A full-adder-based methodology for the design of scaling operation in residue number system
M Dasygenis, K Mitroglou, D Soudris, A Thanailakis
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (2), 546-558, 2008
112008
A memory hierarchical layer assigning and prefetching technique to overcome the memory performance/energy bottleneck
M Dasygenis, E Brockmeyer, B Durinck, F Catthoor, D Soudris, ...
Design, Automation and Test in Europe, 946-947, 2005
102005
A full adder based methodology for scaling operation in residue number system
D Soudris, M Dasygenis, K Mitroglou, K Tatas, A Thanailakis
9th International Conference on Electronics, Circuits and Systems 3, 891-894, 2002
92002
A modified spiral search motion estimation algorithm and its embedded system implementation
N Kroupis, M Dasygenis, K Markou, D Soudris, A Thanailakis
2005 IEEE International Symposium on Circuits and Systems, 3347-3350, 2005
72005
VLSI methodology for the design of RNS and QRNS full adder based converters
DJ Soudris, MM Dasygenis, AT Thanailakis
IEE Proceedings-Circuits, Devices and Systems 149 (4), 241-250, 2002
72002
Implementation of a motion estimation hardware accelerator on Zynq SoC
T Makryniotis, M Dasygenis
2017 6th International Conference on Modern Circuits and Systems …, 2017
52017
A novel division algorithm for parallel and sequential processing
K Tatas, DJ Soudris, D Siomos, M Dasygenis, A Thanailakis
9th International Conference on Electronics, Circuits and Systems 2, 553-556, 2002
52002
A Smart Recycling Bin for Waste Classification
D Ziouzios, M Dasygenis
2019 Panhellenic Conference on Electronics & Telecommunications (PACET), 1-4, 2019
42019
A monitoring system for people living with Alzheimer's disease
IM Tabakis, M Dasygenis, M Tsolaki
2017 Panhellenic Conference on Electronics and Telecommunications (PACET), 1-4, 2017
42017
Building portfolios for parallel constraint solving by varying the local consistency applied
M Dasygenis, K Stergiou
2014 IEEE 26th International Conference on Tools with Artificial …, 2014
42014
A unique network EDA tool to create optimized ad hoc binary to residue number system converters
G Petrousov, M Dasygenis
2014 24th International Workshop on Power and Timing Modeling, Optimization …, 2014
42014
A Smart Bin Implementantion using LoRa
D Ziouzios, M Dasygenis
2019 4th South-East Europe Design Automation, Computer Engineering, Computer …, 2019
32019
Autonomous obstacle avoidance vehicle using LIDAR and an embedded system
N Baras, G Nantzios, D Ziouzios, M Dasygenis
2019 8th International Conference on Modern Circuits and Systems …, 2019
32019
A portable image processing accelerator using FPGA
D Tsiktsiris, D Ziouzios, M Dasygenis
2018 7th International Conference on Modern Circuits and Systems …, 2018
32018
An internet of things humanoid robot teleoperated by an open source android application
G Angelopoulos, GT Kalampokis, M Dasygenis
2017 Panhellenic Conference on Electronics and Telecommunications (PACET), 1-4, 2017
32017
Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor
A Sideris, T Sanida, M Dasygenis
2019 8th International Conference on Modern Circuits and Systems …, 2019
22019
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Articles 1–20