| Scalable video coding deblocking filter FPGA and ASIC implementation using high-level synthesis methodology PP Carballo, O Espino, R Neris, P Hernandez-Fernandez, TM Szydzik, ... Digital System Design (DSD), 2013 Euromicro Conference on, 415-422, 2013 | 8 | 2013 |
| ESL flow for a hardware H. 264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study M Thadani, PP Carballo, P Hernández, G Marrero, A Núñez SPIE Europe Microtechnologies for the New Millennium, 73630K-73630K-12, 2009 | 6 | 2009 |
| SystemC modelling of lossless compression IP cores for space applications L Santos, A Gómez, P Hernández-Fernández, R Sarmiento 2016 Conference on Design and Architectures for Signal and Image Processing …, 2016 | 2 | 2016 |
| TCP/IP Packet Analyzer on a Zynq Platform B Vega, PP Carballo, P Hernández-Fernández, A Domínguez, A Núñez. Euromicro DSD/SEAA 2015, 2015 | 2 | 2015 |
| Quantitative assessment of the optimization steps in an ESL flow for a hardware implementation of a H.264/AVC decoder M Thadani, T Szydzik, PP Carballo, P Hernández-Fernández, GM Callicó, ... Proceedings of the 16th Euromicro Conference on Digital System Design, DSD …, 2009 | 2 | 2009 |
| Implementation of scalable video coding deblocking filter from high-level SystemC description PP Carballo, O Espino, R Neris, P Hernández-Fernández, TM Szydzik, ... SPIE Microtechnologies, 876408-876408-10, 2013 | | 2013 |
| Transaction Level Modeling for a Super-Resolution Hardware-Engine Design A Sánchez-Peña, P Hernández, G P. Carballo, M Callicó, A Núñez. XXIII Conference on Design of Circuits and Integrated Systems (DCIS’08), 2008 | | 2008 |
