Gururaj Saileshwar
Gururaj Saileshwar
PhD Student, ECE, Georgia Tech
Verified email at gatech.edu - Homepage
TitleCited byYear
Synergy: Rethinking secure-memory design for error-correcting memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, MK Qureshi
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
152018
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
G Saileshwar, P Nair, P Ramrakhyani, W Elsasser, J Joao, M Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
102018
CMOS low-noise signal conditioning with a novel differential “resistance to frequency” converter for resistive sensor applications
P Kabara, S Thakur, G Saileshwar, MS Baghini, DK Sharma
2011 International SoC Design Conference, 298-301, 2011
62011
CleanupSpec: An Undo Approach to Safe Speculation
G Saileshwar, MK Qureshi
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
22019
Lookout for Zombies: Mitigating Flush+ Reload Attack on Shared Caches by Monitoring Invalidated Lines
G Saileshwar, MK Qureshi
arXiv preprint arXiv:1906.02362, 2019
2019
Memory organization for security and reliability
G Saileshwar, PS Ramrakhyani, WA Elsasser
US Patent App. 15/668,322, 2019
2019
Probabilistic Integrity for Low-Overhead Secure Memories
G Saileshwar, MK Qureshi
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