| Low temperature implementation of dopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs G Larrieu, E Dubois, R Valentin, N Breil, F Danneville, G Dambrine, ... 2007 IEEE International Electron Devices Meeting, 147-150, 2007 | 278 | 2007 |
| Arsenic-segregated rare-earth silicide junctions: reduction of Schottky barrier and integration in metallic n-MOSFETs on SOI G Larrieu, DA Yarekha, E Dubois, N Breil, O Faynot IEEE Electron Device Letters 30 (12), 1266-1268, 2009 | 266 | 2009 |
| High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ... 2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014 | 179 | 2014 |
| Challenges of nickel silicidation in CMOS technologies N Breil, C Lavoie, A Ozcan, F Baumann, N Klymko, K Nummy, B Sun, ... Microelectronic Engineering 137, 79-87, 2015 | 47 | 2015 |
| Comparative analysis of semiconductor device architectures for 5-nm node and beyond P Feng, SC Song, G Nallapati, J Zhu, J Bao, V Moroz, M Choi, XW Lin, ... IEEE Electron Device Letters 38 (12), 1657-1660, 2017 | 40 | 2017 |
| RF small-signal analysis of Schottky-barrier p-MOSFET R Valentin, E Dubois, JP Raskin, G Larrieu, G Dambrine, TC Lim, N Breil, ... IEEE transactions on electron devices 55 (5), 1192-1202, 2008 | 40 | 2008 |
| Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes CN Ni, KV Rao, F Khaja, S Sharma, S Tang, JJ Chen, KE Hollar, N Breil, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 38 | 2016 |
| Contacts in advanced CMOS: History and emerging challenges C Lavoie, P Adusumilli, AV Carr, JSJ Sweet, AS Ozcan, E Levrau, N Breil, ... ECS Transactions 77 (5), 59, 2017 | 35 | 2017 |
| FinFET source-drain merged by silicide-based material BA Anderson, N Breil, C Lavoie US Patent 9,595,524, 2017 | 33 | 2017 |
| Ti and NiPt/Ti liner silicide contacts for advanced technologies P Adusumilli, E Alptekin, M Raymond, N Breil, F Chafik, C Lavoie, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 30 | 2016 |
| Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and solid-phase epitaxial regrowth (SPER) YR Yang, N Breil, CY Yang, J Hsieh, F Chiang, B Colombeau, BN Guo, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 27 | 2016 |
| Optimization of RF performance of metallic source/drain SOI MOSFETs using dopant segregation at the Schottky interface RË Valentin, E Dubois, G Larrieu, JP Raskin, G Dambrine, N Breil, ... IEEE electron device letters 30 (11), 1197-1199, 2009 | 25 | 2009 |
| Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures N Breil, A Carr, T Kuratomi, C Lavoie, IC Chen, M Stolfi, KD Chiu, W Wang, ... 2017 Symposium on VLSI Technology, T216-T217, 2017 | 23 | 2017 |
| An 8-bit 20.7 TOPS/W multi-level cell ReRAM-based compute engine JM Correll, L Jie, S Song, S Lee, J Zhu, W Tang, L Wormald, J Erhardt, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 22 | 2022 |
| Transistor and method of forming same VS Basker, NL Breil, O Gluschenkov, S Mochizuki, A Reznicek US Patent 9,911,849, 2018 | 22 | 2018 |
| FinFET source-drain merged by silicide-based material BA Anderson, N Breil, C Lavoie US Patent 9,543,167, 2017 | 19 | 2017 |
| Fluorine-free tungsten films as low resistance liners for tungsten fill applications J Bakke, Y Lei, Y Xu, K Daito, X Fu, G Jian, K Wu, R Hung, R Jakkaraju, ... 2016 IEEE International Interconnect Technology Conference/Advanced …, 2016 | 16 | 2016 |
| Oxide mediated epitaxial nickel disilicide alloy contact formation E Alptekin, NL Breil, C Lavoie, AS Ozcan, KT Schonenberg US Patent 9,236,345, 2016 | 14 | 2016 |
| Impact of channel doping on Schottky barrier height and investigation on p-SB MOSFETs performance G Larrieu, E Dubois, D Yarekha, N Breil, N Reckinger, X Tang, ... Materials Science and Engineering: B 154, 159-162, 2008 | 13 | 2008 |
| Selective etching of Pt with respect to PtSi using a sacrificial low temperature germanidation process N Breil, A Halimaoui, T Skotnicki, E Dubois, G Larrieu, A Łaszcz, ... Applied Physics Letters 91 (23), 2007 | 13 | 2007 |
