Alejandro Nocua Cifuentes
Alejandro Nocua Cifuentes
LIRMM - CNRS / University of Montpellier
Verified email at lirmm.fr
TitleCited byYear
ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems
A Nocua, F Bruguier, G Sassatelli, A Gamatie
2017 12th International Symposium on Reconfigurable Communication-centric …, 2017
62017
A Hybrid Power Estimation Technique to improve IP power models quality
A Nocua, A Virazel, A Bosio, P Girard, C Chevalier
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
22016
A hybrid power modeling approach to enhance high-level power models
A Nocua, A Virazel, A Bosio, P Girard, C Chevalier
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
22016
Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study
A Gamatié, A Nocua, J Weloli, G Sassatelli, L Torres, D Novo, M Robert
12019
A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads
A Nocua, F Bruguier, G Sassatelli, A Gamatié
Microprocessors and Microsystems 67, 42-55, 2019
2019
Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing
D Novo, A Nocua, F Bruguier, A Gamatie, G Sassatelli
2018 13th International Symposium on Reconfigurable Communication-centric …, 2018
2018
Trace-driven simulation of multithreaded applications in gem5
G Sassatelli, A Nocua, F Bruguier, A Butko
2017
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization
A Nocua, A Virazel, A Bosio, P Girard, C Chevalier
Journal of Circuits, Systems and Computers 26 (08), 1740004, 2017
2017
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization
A Virazel, A Nocua, A Bosio, P Girard, C Chevalier
2017
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality
A Nocua, A Virazel, A Bosio, P Girard, C Chevalier
Journal of Low Power Electronics 13 (1), 10-28, 2017
2017
An efficient hybrid power modeling approach for accurate gate-level power estimation
A Nocua, A Virazel, A Bosio, P Girard, C Chevalier
2015 27th International Conference on Microelectronics (ICM), 17-20, 2015
2015
Screening small-delay defects using inter-path correlation to reduce reliability risk
JL García-Gervacio, A Nocua, V Champac
Microelectronics Reliability 55 (6), 1005-1011, 2015
2015
MB3 D3. 7–Final Report on Memory Hierarchy Investigations. Version 1.0
A Gamatie, A Nocua, RP Oliveira, PS AVL
www. aspbs. com/jolpe
JP Oliver, F Veirano, D Bouvier, E Boemo, A Nocua, A Virazel, A Bosio, ...
Recent Advances in Low Power Asynchronous Circuit Design 280, 297, 0
A Hybrid Power Modeling Approach To Improve High-Level Power Characterization
A Nocua, A Virazel, A Bosio, P Girard
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