| Semiconductor device comprising buried channel region and method for manufacturing the same S Matsuda, A Azuma US Patent App. 10/602,066, 2004 | 126 | 2004 |
| RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology B Walsh, H Utomo, E Leobandung, A Mahorowala, D Mocuta, K Miyamoto, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 170-171, 2006 | 96 | 2006 |
| Semiconductor device comprising buried channel region S Matsuda, A Azuma US Patent 6,642,581, 2003 | 87 | 2003 |
| High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005 | 85 | 2005 |
| High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide S Inaba, K Okano, S Matsuda, M Fujiwara, A Hokazono, K Adachi, ... IEEE Transactions on Electron Devices 49 (12), 2263-2270, 2002 | 74 | 2002 |
| Low‐loss epitaxial ZnO optical waveguides on sapphire by rf magnetron sputtering MS Wu, A Azuma, T Shiosaki, A Kawabata Journal of applied physics 62 (6), 2482-2484, 1987 | 72 | 1987 |
| Molecular Basis for G2 Arrest Induced by 2′-C-Cyano-2′-Deoxy-1-β-d-Arabino-Pentofuranosylcytosine and Consequences of Checkpoint Abrogation X Liu, Y Guo, Y Li, Y Jiang, S Chubb, A Azuma, P Huang, A Matsuda, ... Cancer research 65 (15), 6874-6881, 2005 | 52 | 2005 |
| High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE S Inaba, K Okano, S Matsuda, M Fujiwara, A Hokazono, K Adachi, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 51 | 2001 |
| Low-loss ZnO optical waveguides for SAW-AO applications MS Wu, A Azuma, T Shiosaki, A Kawabata IEEE transactions on ultrasonics, ferroelectrics, and frequency control 36 …, 1989 | 45 | 1989 |
| Semiconductor device and method of manufacturing the same including thicker insulating layer on lower part of electrode A Azuma, S Matsuda US Patent 6,515,320, 2003 | 33* | 2003 |
| A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond N Yasutake, T Ishida, K Ohuchi, N Aoki, N Kusunoki, S Mori, I Mizushima, ... 2006 European Solid-State Device Research Conference, 77-80, 2006 | 29 | 2006 |
| Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond Y Hiura, A Azuma, K Nakajima, Y Akasaka, K Miyano, H Nitta, A Honjo, ... International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 26 | 1998 |
| In situ doped embedded-SiGe source/drain technique for 32 nm node p-channel metal–oxide–semiconductor field-effect transistor H Okamoto, A Hokazono, K Adachi, N Yasutake, H Itokawa, S Okamoto, ... Japanese journal of applied physics 47 (4S), 2564, 2008 | 24 | 2008 |
| Semiconductor device having gate electrode of stacked structure including polysilicon layer and metal layer and method of manufacturing the same K Ohuchi, A Azuma US Patent 6,642,585, 2003 | 22 | 2003 |
| A novel 0.15/spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions MT Takagi, K Miyashita, H Koyama, K Nakajima, K Miyano, Y Akasaka, ... International Electron Devices Meeting. Technical Digest, 455-458, 1996 | 22 | 1996 |
| Performance improvement of metal gate CMOS technologies S Matsuda, H Yamakawa, A Azuma, Y Toyoshima 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2001 | 21 | 2001 |
| Record-high performance 32 nm node pMOSFET with advanced two-step recessed SiGe-S/D and stress liner technology N Yasutake, A Azuma, T Ishida, N Kusunoki, S Mori, H Itokawa, ... 2007 IEEE Symposium on VLSI Technology, 48-49, 2007 | 17 | 2007 |
| Methodology of mosfet characteristics fluctuation description using bsim3v3 spice model for statistical circuit simulations A Azuma, A Oishi, Y Okayama, K Kasai, Y Toyoshima IWSM. 1998 3rd International Workshop on Statistical Metrology (Cat. No …, 1998 | 17 | 1998 |
| A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process S Hasegawa, Y Kitamura, K Takahata, H Okamoto, T Hirai, K Miyashita, ... 2008 IEEE International Electron Devices Meeting, 1-3, 2008 | 15 | 2008 |
| Semiconductor device having gate electrode of staked structure including polysilicon layer and metal layer and method of manufacturing the same K Ohuchi, A Azuma US Patent App. 11/109,784, 2005 | 14 | 2005 |
