Farzaneh Zokaee
Farzaneh Zokaee
Ph.D. student, Indiana University
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Cited by
Cited by
Aligner: A process-in-memory architecture for short read alignment in rerams
F Zokaee, HR Zarandi, L Jiang
IEEE Computer Architecture Letters 17 (2), 237-240, 2018
LightBulb: A photonic-nonvolatile-memory-based accelerator for binarized convolutional neural networks
F Zokaee, Q Lou, N Youngblood, W Liu, Y Xie, L Jiang
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
Finder: Accelerating fm-index-based exact pattern matching in genomic sequences through reram technology
F Zokaee, M Zhang, L Jiang
2019 28th International Conference on Parallel Architectures and Compilation …, 2019
Magma: A monolithic 3D vertical heterogeneous ReRAM-based main memory architecture
F Zokaee, M Zhang, X Ye, D Fan, L Jiang
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
Designing a differential 3r-2bit rram cell for enhancing read margin in cross-point rram arrays
M Nakhkash, H Bardareh, F Zokaee, HR Zarandi
2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2017
Mitigating voltage drop in resistive memories by dynamic reset voltage regulation and partition reset
F Zokaee, L Jiang
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
Exma: A genomics accelerator for exact-matching
L Jiang, F Zokaee
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators
F Zokaee, L Jiang
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021
A novel SAT-based ATPG approach for transition delay faults
F Zokaee, H Sabaghian-Bidgoli, V Janfaza, P Behnam, Z Navabi
2017 IEEE International High Level Design Validation and Test Workshop …, 2017
A new structure for interconnect offline testing
S Sadeghi-Kohan, S Keshavarz, F Zokaee, F Farahmandi, Z Navabi
East-West Design & Test Symposium (EWDTS 2013), 1-5, 2013
A High Performance, Multi-Bit Output Logic-in-Memory Adder
J Talafy, F Zokaee, HR Zarandi, N Bagherzadeh
IEEE Transactions on Emerging Topics in Computing, 2020
Sky-sorter: A Processing-in-Memory Architecture for Large-Scale Sorting
F Zokaee, F Chen, G Sun, L Jiang
IEEE Transactions on Computers, 2022
FeFET-based Process-in-Memory Architecture for Low-Power DNN Training
F Zokaee, B Li, F Chen
2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 1-6, 2021
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