Matt Horsnell
Title
Cited by
Cited by
Year
The ARM scalable vector extension
N Stephens, S Biles, M Boettcher, J Eapen, M Eyole, G Gabrielli, ...
IEEE micro 37 (2), 26-39, 2017
1402017
An adaptive bloom filter cache partitioning scheme for multicore architectures
K Nikas, M Horsnell, J Garside
2008 International Conference on Embedded Computer Systems: Architectures†…, 2008
282008
Cryptographic support instructions
MJ Horsnell, RR Grisenthwaite, D Kershaw, SD Biles
US Patent 8,966,282, 2015
212015
Data processing apparatus and method and method for generating performance monitoring interrupt signal based on first event counter and second event counter
MJ Horsnell, CD Emmons
US Patent 9,021,172, 2015
182015
An object-aware hardware transactional memory system
B Khan, M Horsnell, I Rogers, M LujŠn, A Dinn, I Watson
2008 10th IEEE International Conference on High Performance Computing and†…, 2008
152008
Evaluation of hybrid run-time power models for the ARM big. LITTLE architecture
K Nikov, JL Nunez-Yanez, M Horsnell
2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing†…, 2015
132015
Optimizing chip multiprocessor work distribution using dynamic compilation
J Zhao, M Horsnell, I Rogers, A Dinn, C Kirkham, I Watson
European Conference on Parallel Processing, 258-267, 2007
92007
Adaptive loop tiling for a multi-cluster cmp
J Zhao, M Horsnell, M LujŠn, I Rogers, C Kirkham, I Watson
International Conference on Algorithms and Architectures for Parallel†…, 2008
72008
Flexible and high-speed system-level performance analysis using hardware-accelerated simulation
S Bischoff, A Sandberg, A Hansson, S Dam, A Saidi, M Horsnell, ...
Design, Automation & Test in Europe (DATE), 18-22 Match, 2013, Grenoble, France, 2013
62013
A chip multi-cluster architecture with locality aware task distribution
MJ Horsnell
PQDT-Global, 2007
52007
A first insight into object-aware hardware transactional memory
B Khan, M Horsnell, I Rogers, M LujŠn, A Dinn, I Watson
Proceedings of the twentieth annual symposium on Parallelism in algorithms†…, 2008
42008
Debugging data processing transactions
S Diestelhorst, MJ Williams, RR Grisenthwaite, MJ Horsnell
US Patent 10,394,557, 2019
32019
Matthew Horsnell. Jim Garside. 2008. An Adaptive Bloom Filter Cache Partitioning Scheme for Multi-Core Architectures
K Nikas
Proceedings of the IEEE International Conference on Embedded Computer†…, 0
3
Scalable object-aware hardware transactional memory
B Khan, M Horsnell, M Lujan, I Watson
European Conference on Parallel Processing, 268-279, 2010
22010
Monitoring utilization of transactional processing resource
S Diestelhorst, MJ Horsnell
US Patent 10,810,039, 2020
12020
Vulnerability determination in circuits
V Balaji, R Jeyapaul, X Iturbe, MJ Horsnell, DM Gilday
US Patent 10,523,186, 2019
12019
Cryptographic support instructions
MJ Horsnell, RR Grisenthwaite, SD Biles, D Kershaw
US Patent 9,104,400, 2015
12015
Transactional compare-and-discard instruction
MJ Horsnell, G Magklis, S Diestelhorst
US Patent App. 17/258,287, 2021
2021
Circuitry and methods
R GRUBISIC, G GABRIELLI, MJ HORSNELL, SAM Zaidi
US Patent App. 16/662,396, 2021
2021
Exception handling in transactions
MJ HORSNELL, G Magklis, S Diestelhorst
US Patent App. 17/046,396, 2021
2021
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