| The ARM scalable vector extension N Stephens, S Biles, M Boettcher, J Eapen, M Eyole, G Gabrielli, ... IEEE micro 37 (2), 26-39, 2017 | 241 | 2017 |
| An adaptive bloom filter cache partitioning scheme for multicore architectures K Nikas, M Horsnell, J Garside 2008 International Conference on Embedded Computer Systems: Architectures …, 2008 | 28 | 2008 |
| Cryptographic support instructions MJ Horsnell, RR Grisenthwaite, D Kershaw, SD Biles US Patent 8,966,282, 2015 | 24 | 2015 |
| Data processing apparatus and method and method for generating performance monitoring interrupt signal based on first event counter and second event counter MJ Horsnell, CD Emmons US Patent 9,021,172, 2015 | 21 | 2015 |
| Evaluation of hybrid run-time power models for the ARM big. LITTLE architecture K Nikov, JL Nunez-Yanez, M Horsnell 2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing …, 2015 | 16 | 2015 |
| An object-aware hardware transactional memory system B Khan, M Horsnell, I Rogers, M Luján, A Dinn, I Watson 2008 10th IEEE International Conference on High Performance Computing and …, 2008 | 16 | 2008 |
| Speculation barrier instruction RR Grisenthwaite, G Gabrielli, MJ Horsnell US Patent 10,866,805, 2020 | 9 | 2020 |
| Optimizing chip multiprocessor work distribution using dynamic compilation J Zhao, M Horsnell, I Rogers, A Dinn, C Kirkham, I Watson Euro-Par, 258-267, 2007 | 8 | 2007 |
| Adaptive loop tiling for a multi-cluster cmp J Zhao, M Horsnell, M Luján, I Rogers, C Kirkham, I Watson Algorithms and Architectures for Parallel Processing: 8th International …, 2008 | 7 | 2008 |
| Flexible and high-speed system-level performance analysis using hardware-accelerated simulation S Bischoff, A Sandberg, A Hansson, S Dam, A Saidi, M Horsnell, ... Design, Automation & Test in Europe (DATE), 18-22 Match, 2013, Grenoble, France, 2013 | 6 | 2013 |
| Apparatus with shared transactional processing resource, and data processing method S Diestelhorst, MJ Horsnell, G Larri US Patent 10,908,944, 2021 | 5 | 2021 |
| A chip multi-cluster architecture with locality aware task distribution MJ Horsnell PQDT-Global, 2007 | 5 | 2007 |
| Handling of inter-element address hazards for vector instructions MJ Horsnell, M Eyole US Patent 10,922,084, 2021 | 4 | 2021 |
| Debugging data processing transactions S Diestelhorst, MJ Williams, RR Grisenthwaite, MJ Horsnell US Patent 10,394,557, 2019 | 4 | 2019 |
| A first insight into object-aware hardware transactional memory B Khan, M Horsnell, I Rogers, M Luján, A Dinn, I Watson Proceedings of the twentieth annual symposium on Parallelism in algorithms …, 2008 | 4 | 2008 |
| Electronic authentication system, device and process D Croxford, RL Mendez, M Eyole, MJ Horsnell US Patent App. 17/429,222, 2022 | 3 | 2022 |
| Matthew Horsnell. Jim Garside. 2008. An Adaptive Bloom Filter Cache Partitioning Scheme for Multi-Core Architectures K Nikas Proceedings of the IEEE International Conference on Embedded Computer …, 0 | 3 | |
| Address translation data invalidation MJ Horsnell, G Magklis, RR Grisenthwaite US Patent App. 16/625,102, 2020 | 2 | 2020 |
| Scalable object-aware hardware transactional memory B Khan, M Horsnell, M Lujan, I Watson Euro-Par 2010-Parallel Processing: 16th International Euro-Par Conference …, 2010 | 2 | 2010 |
| Authentication system, device and process M Eyole, MJ Horsnell US Patent App. 16/271,760, 2020 | 1 | 2020 |
Mikel LujanDepartment of Computer Science, University of ManchesterVerified email at manchester.ac.uk
