Jean-Luc Autran
Jean-Luc Autran
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TítuloCitado porAño
Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications
C Chaneliere, JL Autran, RAB Devine, B Balland
Materials Science and Engineering: R: Reports 22 (6), 269-322, 1998
Properties of amorphous and crystalline thin films deposited on Si from a precursor
C Chaneliere, S Four, JL Autran, RAB Devine, NP Sandler
Journal of applied physics 83 (9), 4823-4829, 1998
Influence of band-structure on electron ballistic transport in Silicon nanowire MOSFET's: an atomistic study
K Nehari, N Cavassilas, JL Autran, M Bescond, D Munteanu, M Lannoo
Proceedings of 35th European Solid-State Device Research Conference, 2005 …, 2005
75 nm damascene metal gate and high-k integration for advanced CMOS devices
B Guillaumot, X Garros, F Lime, K Oshima, B Tavel, JA Chroboczek, ...
Digest. International Electron Devices Meeting,, 355-358, 2002
Modeling and simulation of single-event effects in digital devices and ICs
D Munteanu, JL Autran
IEEE Transactions on Nuclear science 55 (4), 1854-1878, 2008
On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs
P Masson, JL Autran, J Brini
IEEE Electron Device Letters 20 (2), 92-94, 1999
Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices
D Munteanu, JL Autran
Solid-State Electronics 47 (7), 1219-1225, 2003
Quantum short-channel compact modelling of drain-current in double-gate MOSFET
D Munteanu, JL Autran, X Loussier, S Harrison, R Cerutti, T Skotnicki
Solid-state electronics 50 (4), 680-686, 2006
Technology downscaling worsening radiation effects in bulk: SOI to the rescue
P Roche, JL Autran, G Gasiot, D Munteanu
2013 IEEE International Electron Devices Meeting, 31.1. 1-31.1. 4, 2013
Interfacial hardness enhancement in deuterium annealed 0.25 μm channel metal oxide semiconductor transistors
RAB Devine, JL Autran, WL Warren, KL Vanheusdan, JC Rostaing
Applied Physics Letters 70 (22), 2999-3001, 1997
Frequency characterization and modeling of interface traps in gate dielectric stack from a capacitance point-of-view
P Masson, JL Autran, M Houssa, X Garros, C Leroux
Applied Physics Letters 81 (18), 3392-3394, 2002
Scanning nonlinear dielectric microscopy nano-science and technology for next generation high density ferroelectric data storage
K Tanaka, Y Kurihashi, T Uda, Y Daimon, N Odagawa, R Hirose, ...
Japanese Journal of Applied Physics 47 (5R), 3311, 2008
Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2gate stack
V Barral, T Poiroux, F Andrieu, C Buj-Dufournet, O Faynot, T Ernst, ...
2007 IEEE International Electron Devices Meeting, 61-64, 2007
Conduction mechanisms in and stacked structures on Si
C Chaneliere, JL Autran, RAB Devine
Journal of applied physics 86 (1), 480-486, 1999
Model for interface defect and positive charge generation in ultrathin gate dielectric stacks
M Houssa, JL Autran, A Stesmans, MM Heyns
Applied Physics Letters 81 (4), 709-711, 2002
Electrical properties of Ta2O5 films obtained by plasma enhanced chemical vapor deposition using a TaF5 source
RAB Devine, L Vallier, JL Autran, P Paillet, JL Leray
Applied physics letters 68 (13), 1775-1777, 1996
Heavy ion testing and 3D simulations of Multiple Cell Upset in 65nm standard SRAMs
D Giot, P Roche, G Gasiot, JL Autran, R Harboe-Sorensen
2007 9th European Conference on Radiation and Its Effects on Components and …, 2007
Fabrication and characterization of Si-MOSFET's with PECVD amorphous Ta 2 O 5 gate insulator
JL Autran, R Devine, C Chaneliere, B Balland
IEEE Electron device letters 18 (9), 447-449, 1997
Single event upset and multiple cell upset modeling in commercial bulk 65-nm CMOS SRAMs and flip-flops
S Uznanski, G Gasiot, P Roche, C Tavernier, JL Autran
IEEE Transactions on Nuclear Science 57 (4), 1876-1883, 2010
3D quantum modeling and simulation of multiple-gate nanowire MOSFETs
M Bescond, K Nehari, JL Autran, N Cavassilas, D Munteanu, M Lannoo
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
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