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Marcelo Antonio Pavanello
Marcelo Antonio Pavanello
Full Professor, Department of Electrical Engineering, Centro Universitário da FEI
Dirección de correo verificada de fei.edu.br - Página principal
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Junctionless multiple-gate transistors for analog applications
RT Doria, MA Pavanello, RD Trevisoli, M de Souza, CW Lee, I Ferain, ...
IEEE Transactions on Electron Devices 58 (8), 2511-2519, 2011
2852011
Caracterização elétrica de tecnologia e dispositivos MOS
PB Verdonck
Cengage Learning Editores, 2004
1582004
Threshold voltage in junctionless nanowire transistors
RD Trevisoli, RT Doria, M de Souza, MA Pavanello
Semiconductor Science and Technology 26 (10), 105009, 2011
1322011
Analog performance and application of graded-channel fully depleted SOI MOSFETs
MA Pavanello, JA Martino, V Dessard, D Flandre
Solid-State Electronics 44 (7), 1219-1222, 2000
1312000
Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors
RD Trevisoli, RT Doria, M de Souza, S Das, I Ferain, MA Pavanello
IEEE Transactions on Electron Devices 59 (12), 3510-3518, 2012
1272012
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
MA Pavanello, JA Martino, D Flandre
Solid-State Electronics 44 (6), 917-922, 2000
1142000
An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics
MA Pavanello, JA Martino, V Dessard, D Flandre
Electrochemical and Solid-State Letters 3 (1), 50, 1999
781999
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
A Cerdeira, MA Alemán, MA Pavanello, JA Martino, L Vancaillie, ...
IEEE Transactions on Electron Devices 52 (5), 967-972, 2005
672005
Impact of the series resistance in the IV characteristics of junctionless nanowire transistors and its dependence on the temperature
RT Doria, RD Trevisoli, M de Souza, MA Pavanello
Journal of Integrated Circuits and Systems 7 (2), 121-129, 2012
652012
Cryogenic operation of junctionless nanowire transistors
M de Souza, MA Pavanello, RD Trevisoli, RT Doria, JP Colinge
IEEE Electron Device Letters 32 (10), 1322-1324, 2011
622011
A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors
RD Trevisoli, RT Doria, M de Souza, MA Pavanello
Solid-State Electronics 90, 12-17, 2013
582013
Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
MA Pavanello, JA Martino, D Flandre
Solid-State Electronics 46 (8), 1215-1225, 2002
542002
Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation
MA Pavanello, JA Martino, E Simoen, R Rooyackers, N Collaert, C Claeys
Solid-State Electronics 51 (2), 285-291, 2007
512007
Charge-based continuous model for long-channel symmetric double-gate junctionless transistors
A Cerdeira, M Estrada, B Iniguez, RD Trevisoli, RT Doria, M De Souza, ...
Solid-State Electronics 85, 59-63, 2013
472013
Charge-based compact analytical model for triple-gate junctionless nanowire transistors
F Ávila-Herrera, BC Paz, A Cerdeira, M Estrada, MA Pavanello
Solid-State Electronics 122, 23-31, 2016
462016
The zero temperature coefficient in junctionless nanowire transistors
R Doria Trevisoli, R Trevisoli Doria, M de Souza, S Das, I Ferain, ...
Applied Physics Letters 101 (6), 2012
402012
An explicit multi-exponential model for semiconductor junctions with series and shunt resistances
D Lugo-Munoz, J Muci, A Ortiz-Conde, FJ Garcia-Sanchez, M De Souza, ...
Microelectronics Reliability 51 (12), 2044-2048, 2011
402011
Double-gate junctionless transistor model including short-channel effects
BC Paz, F Ávila-Herrera, A Cerdeira, MA Pavanello
Semiconductor science and technology 30 (5), 055011, 2015
382015
Substrate bias influence on the operation of junctionless nanowire transistors
R Trevisoli, RT Doria, M de Souza, MA Pavanello
IEEE Transactions on Electron Devices 61 (5), 1575-1582, 2014
382014
Direct determination of threshold condition in DG-MOSFETs from the gm/ID curve
AIA Cunha, MA Pavanello, RD Trevisoli, C Galup-Montoro, MC Schneider
Solid-State Electronics 56 (1), 89-94, 2011
362011
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Artículos 1–20