A 68.6fsrms -total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
17 2022 A 12.9-to-15.1 GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6 fs Integrated Jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021
14 2021 A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ...
IEEE Journal of Solid-State Circuits, 2021
12 2021 32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021
10 2021 A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...
IEEE Journal of Solid-State Circuits, 2022
8 2022 4.5 A 9.25 GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology G Castoro, SM Dartizio, F Tesolin, F Buccoleri, M Rossoni, D Cherniak, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 82-84, 2023
7 2023 4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering SM Dartizio, F Tesolin, G Castoro, F Buccoleri, L Lanzoni, M Rossoni, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 3-5, 2023
7 2023 A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Lesurum, ...
2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022
5 2022 A 72-fs-Total-Integrated-Jitter Two-Core Fractional- F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...
IEEE Journal of Solid-State Circuits, 2022
3 2022 Phase Noise Analysis of Periodically ON/OFF Switched Oscillators G Castoro, SM Dartizio, AL Lacaita, S Levantino
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
2 2022 A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays F Tesolin, SM Dartizio, F Buccoleri, A Santiccioli, L Bertulessi, C Samori, ...
IEEE Journal of Solid-State Circuits, 2023
1 2023 10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion F Tesolin, SM Dartizio, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 198-200, 2024
2024 10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM M Rossoni, SM Dartizio, F Tesolin, G Castoro, R Dell’Orto, C Samori, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 188-190, 2024
2024 A Low-Spur and Low-Jitter Fractional- SM Dartizio, F Tesolin, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ...
IEEE Journal of Solid-State Circuits, 2023
2023 