Josep M. Codina
TitleCited byYear
Graph-partitioning based instruction scheduling for clustered processors
A Aletŕ, JM Codina, J Sánchez, A González
Proceedings of the 34th annual ACM/IEEE international symposium on …, 2001
832001
A unified modulo scheduling and register allocation technique for clustered processors
JM Codina, J Sánchez, A González
Proceedings 2001 International Conference on Parallel Architectures and …, 2001
682001
Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution
F Latorre, JM Codina, EG Codina, P Lopez, C Madriles, AM Vincente, ...
US Patent 8,909,902, 2014
662014
Register checkpointing mechanism for multithreading
P Lopez, C Madriles, A Martinez, R Martinez, JM Codina, EG Codina, ...
US Patent App. 12/420,762, 2010
602010
Register Checkpointing Mechanism For Multithreading
AG Pedro Lopez, Carlos Madriles, Alejandro Martinez, Raul Martinez, Josep M ...
US Patent 20,100,262,812, 2010
60*2010
A comparative study of modulo scheduling techniques
JM Codina, J Llosa, A González
Proceedings of the 16th international conference on Supercomputing, 97-106, 2002
602002
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
C Madriles, P López, JM Codina, E Gibert, F Latorre, A Martínez, ...
ACM SIGARCH Computer Architecture News 37 (3), 474-483, 2009
422009
Instruction and logic for optimization level aware branch prediction
P Xekalakis, P Marcuello, AV Martinez, CE Kotselidis, G Magklis, ...
US Patent 10,157,063, 2018
33*2018
Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region
R Martinez, EG Codina, P Lopez, MT Lapuerta, P Xekalakis, G Tournavitis, ...
US Patent 10,013,326, 2018
332018
Exploiting pseudo-schedules to guide data dependence graph partitioning
A Aletŕ, JM Codina, J Sánchez, A González, D Kaeli
Proceedings. International Conference on Parallel Architectures and …, 2002
322002
Cache sharing based thread control
A Gonzalez, JM Codina, P Lopez, F Latorre, JA Pineiro, E Gibert, J Abella, ...
US Patent 7,895,415, 2011
272011
Instruction replication for clustered microarchitectures
A Aletŕ, JM Codina, A González, D Kaeli
Proceedings of the 36th annual IEEE/ACM International Symposium on …, 2003
272003
Access of register files of other threads using synchronization
E Gibert, JM Codina, F Latorre, JA Pińeiro, P López, A González
US Patent 8,261,046, 2012
252012
Profiling asynchronous events resulting from the execution of software at code region granularity
R Martinez, EG Codina, P Lopez, MT Lapuerta, P Xekalakis, G Tournavitis, ...
US Patent App. 13/993,054, 2013
232013
AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures
A Aleta, JM Codina, J Sánchez, A González, D Kaeli
IEEE Transactions on computers 58 (6), 770-783, 2009
222009
Anaphase: A fine-grain thread decomposition scheme for speculative multithreading
C Madriles, P Lopez, JM Codina, E Gibert, F Latorre, A Martinez, ...
2009 18th International Conference on Parallel Architectures and Compilation …, 2009
212009
Heterogeneous clustered VLIW microarchitectures
A Aleta, JM Codina, A Gonzalez, D Kaeli
Proceedings of the International Symposium on Code Generation and …, 2007
212007
Replacement policy for hot code detection
P Lopez, FJ Sánchez, JM Codina, E Gibert, F Latorre, G Magklis, ...
US Patent 8,612,698, 2013
182013
Replacement Policy for Hot Code Detection
AG Pedro Lopez, F. Jesus Sanchez, Josep M. Codina, Enric Gibert, Fernando ...
US Patent 20,100,115,247, 2010
18*2010
Achieving coherence between dynamically optimized code and original code
F Latorre, G Magklis, E Gibert, JM Codina, A González
US Patent 8,190,652, 2012
172012
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