| Design space exploration for sparse matrix‐matrix multiplication on FPGAs CY Lin, N Wong, HKH So International Journal of Circuit Theory and Applications 41 (2), 205-219, 2013 | 68 | 2013 |
| A model for matrix multiplication performance on FPGAs CY Lin, HKH So, PHW Leong 2011 21st International Conference on Field Programmable Logic and …, 2011 | 28 | 2011 |
| A survey of open source processors for FPGAs R Jia, CY Lin, Z Guo, R Chen, F Wang, T Gao, H Yang 2014 24th International Conference on Field Programmable Logic and …, 2014 | 22 | 2014 |
| A computationally efficient reconfigurable FIR filter architecture based on coefficient occurrence probability R Jia, HG Yang, CY Lin, R Chen, XG Wang, ZH Guo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 21 | 2015 |
| Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis CY Lin, HKHKH So ACM SIGARCH Computer Architecture News 40 (5), 58-63, 2012 | 14 | 2012 |
| A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency C Liu, CL Yu, HKH So 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013 | 13 | 2013 |
| NAND-NOR: A compact, fast, and delay balanced FPGA logic element Z Huang, X Wei, G Zgheib, W Li, Y Lin, Z Jiang, K Tu, P Ienne, H Yang Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 11 | 2017 |
| FPGA high-level synthesis versus overlay: Comparisons on computation kernels CY Lin, Z Jiang, C Fu, HKH So, H Yang ACM SIGARCH Computer Architecture News 44 (4), 92-97, 2017 | 10 | 2017 |
| Exploring architecture parameters for dual-output LUT based FPGAs Z Jiang, CY Lin, L Yang, F Wang, H Yang 2014 24th International Conference on Field Programmable Logic and …, 2014 | 9 | 2014 |
| Operation scheduling for FPGA-based reconfigurable computers CY Lin, N Wong, HKH So 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 7 | 2009 |
| Timing-constrained minimum area/power FPGA memory mapping F Du, CY Lin, X Cui, J Sun, F Liu, F Liu, H Yang 2013 23rd International Conference on Field programmable Logic and …, 2013 | 6 | 2013 |
| A technology mapper for depth-constrained FPGA logic cells Z Jiang, G Zgheib, CY Lin, D Novo, Z Huang, L Yang, H Yang, P Ienne 2015 25th International Conference on Field Programmable Logic and …, 2015 | 5 | 2015 |
| A comparison of SAR image speckle filters S Lang, CY Lin, J Liu, N Wong, HKH So MIPPR 2009: Remote Sensing and GIS Data Processing and Other Applications …, 2009 | 5 | 2009 |
| Low cost 1D DCT core for multiple video codec R Jia, R Chen, CY Lin, Z Guo, H Yang Chinese Journal of Electronics 25 (6), 1052-1057, 2016 | 4 | 2016 |
| Sparse tucker tensor decomposition on a hybrid FPGA–CPU platform W Jiang, K Zhang, CY Lin, F Xing, Z Zhang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 3 | 2020 |
| A semi-supervised modeling approach for performance characterization of FPGA architectures L Yang, H Yang, W Li, Z Li, Z Huang, CY Lin 2014 24th International Conference on Field Programmable Logic and …, 2014 | 3 | 2014 |
| Automatic system architecture synthesis for FPGA-based reconfigurable computers CY Lin, N Wong, HKH So 2009 International Conference on Field-Programmable Technology, 475-476, 2009 | 2 | 2009 |
| Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs CY Lin, N Wong, HKH So Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 1 | 2012 |
| ArchSyn: an energy-efficient FPGA high-level synthesizer 林郁 香港大學, 2012 | 1 | 2012 |
| Power-delay and energy-delay tradeoffs in sparse matrix-matrix multiplication on FPGAs Y Lin, Z Zhang, N Wong, HKH So Proceedings of the International Workshop on Highly Efficient Accelerators …, 2010 | 1 | 2010 |
Hayden Kwok-Hay SoUniveristy of Hong KongDirección de correo verificada de eee.hku.hk
