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Natalia Seoane Iglesias
Natalia Seoane Iglesias
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Year
FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability
D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ...
IEEE Journal of the Electron Devices Society 6, 332-340, 2018
2032018
Quantum-transport study on the impact of channel length and cross sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors
A Martinez, M Aldegunde, N Seoane, AR Brown, JR Barker, A Asenov
IEEE Transactions on Electron Devices 58 (8), 2209-2217, 2011
852011
Current variability in Si nanowire MOSFETs due to random dopants in the source/drain regions: A fully 3-D NEGF simulation study
N Seoane, A Martinez, AR Brown, JR Barker, A Asenov
IEEE Transactions on electron devices 56 (7), 1388-1395, 2009
802009
Implementation of the density gradient quantum corrections for 3-D simulations of multigate nanoscaled transistors
AJ Garcia-Loureiro, N Seoane, M Aldegunde, R Valin, A Asenov, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
782011
Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques
A Asenov, AR Brown, G Roy, B Cheng, C Alexander, C Riddet, U Kovac, ...
Journal of computational electronics 8, 349-373, 2009
752009
Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes
D Nagy, G Espineira, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane
IEEE Access 8, 53196-53202, 2020
702020
Variability in Si nanowire MOSFETs due to the combined effect of interface roughness and random dopants: A fully three-dimensional NEGF simulation study
A Martinez, N Seoane, AR Brown, JR Barker, A Asenov
IEEE Transactions on electron devices 57 (7), 1626-1635, 2010
642010
Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET
N Seoane, G Indalecio, E Comesana, M Aldegunde, AJ Garcia-Loureiro, ...
IEEE Transactions on Electron Devices 61 (2), 466-472, 2013
612013
Advanced simulation of statistical variability and reliability in nano CMOS transistors
A Asenov, S Roy, RA Brown, G Roy, C Alexander, C Riddet, C Millar, ...
2008 IEEE International Electron Devices Meeting, 1-1, 2008
512008
Benchmarking of scaled InGaAs implant-free nanoMOSFETs
K Kalna, N Seoane, AJ Garcia-Loureiro, IG Thayne, A Asenov
IEEE transactions on electron devices 55 (9), 2297-2306, 2008
472008
Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs
N Seoane, G Indalecio, M Aldegunde, D Nagy, MA Elmessary, ...
IEEE Transactions on Electron Devices 63 (3), 1209-1216, 2016
452016
Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations
MA Elmessary, D Nagy, M Aldegunde, N Seoane, G Indalecio, J Lindberg, ...
Solid-State Electronics 128, 17-24, 2017
432017
3-D nonequilibrium Green's function simulation of nonperturbative scattering from discrete dopants in the source and drain of a silicon nanowire transistor
A Martinez, N Seoane, AR Brown, JR Barker, A Asenov
IEEE Transactions on Nanotechnology 8 (5), 603-610, 2009
412009
Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET
G Espineira, D Nagy, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane
IEEE Electron Device Letters 40 (4), 510-513, 2019
342019
Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs
N Seoane, JG Fernandez, K Kalna, E Comesana, A Garcia-Loureiro
IEEE Electron Device Letters 42 (10), 1416-1419, 2021
312021
Study of metal-gate work-function variation using Voronoi cells: Comparison of Rayleigh and gamma distributions
G Indalecio, AJ Garcia-Loureiro, NS Iglesias, K Kalna
IEEE Transactions on Electron Devices 63 (6), 2625-2628, 2016
292016
Vertical-tunnel-junction (VTJ) solar cell for ultra-high light concentrations (> 2000 suns)
EF Fernández, N Seoane, F Almonacid, AJ García-Loureiro
IEEE Electron Device Letters 40 (1), 44-47, 2018
282018
Metal grain granularity study on a gate-all-around nanowire FET
D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ...
IEEE Transactions on Electron Devices 64 (12), 5263-5269, 2017
282017
Reduction of the self-forces in Monte Carlo simulations of semiconductor devices on unstructured meshes
M Aldegunde, N Seoane, AJ García-Loureiro, K Kalna
Computer Physics Communications 181 (1), 24-34, 2010
272010
Study of parallel numerical methods for semiconductor device simulation
N Seoane, AJ García‐Loureiro
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2006
242006
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