Angshuman Parashar
TitleCited byYear
Scnn: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH Computer Architecture News 45 (2), 27-40, 2017
3372017
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
M Pellauer, M Adler, M Kinsy, A Parashar, J Emer
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
1082011
Triggered instructions: a control paradigm for spatially-programmed architectures
A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ...
ACM SIGARCH Computer Architecture News 41 (3), 142-153, 2013
912013
Leap scratchpads: automatic memory and cache management for reconfigurable logic
M Adler, KE Fleming, A Parashar, M Pellauer, J Emer
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
882011
Mechanisms for bounding vulnerabilities of processor structures
NK Soundararajan, A Parashar, A Sivasubramaniam
Proceedings of the 34th annual international symposium on Computer …, 2007
752007
A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy
A Parashar, S Gurumurthi, A Sivasubramaniam
Proceedings. 31st Annual International Symposium on Computer Architecture …, 2004
622004
SlicK: slice-based locality exploitation for efficient redundant multithreading
A Parashar, A Sivasubramaniam, S Gurumurthi
ACM SIGOPS Operating Systems Review 40 (5), 95-105, 2006
552006
Leveraging latency-insensitivity to ease multiple FPGA design
KE Fleming, M Adler, M Pellauer, A Parashar, A Mithal, J Emer
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
492012
Efficient control and communication paradigms for coarse-grained spatial architectures
M Pellauer, A Parashar, M Adler, B Ahsan, R Allmon, N Crago, K Fleming, ...
ACM Transactions on Computer Systems (TOCS) 33 (3), 1-32, 2015
262015
Efficient spatial processing element control via triggered instructions
A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ...
IEEE Micro 34 (3), 120-137, 2014
262014
LEAP: A virtual platform architecture for FPGAs
A Parashar, M Adler, K Fleming, M Pellauer, J Emer
The First Workshop on the Intersections of Computer Architecture and …, 2010
232010
Executing distributed memory operations using processing elements connected by distributed channels
B Ahsan, MC Adler, NC Crago, JS Emer, A Jaleel, A Parashar, ...
US Patent 10,331,583, 2019
212019
Hybrid cpu/fpga performance models
A Parashar, M Adler, M Pellauer, J Emer
3rd Workshop on Architectural Research Prototyping (WARP 2008), 2008
122008
An uncalibrated lightfield acquisition system
P Sharma, A Parashar, S Banerjee, P Kalra
Image and Vision Computing 22 (14), 1197-1202, 2004
112004
Timeloop: A systematic approach to dnn accelerator evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
2019 IEEE International Symposium on Performance Analysis of Systems and …, 2019
72019
Stitch-x: An accelerator architecture for exploiting unstructured sparsity in deep neural networks
CE Lee, YS Shao, JF Zhang, A Parashar, J Emer, SW Keckler, Z Zhang
SysML Conference, 2018
52018
Arvind, and JS Emer,“
K Fleming, M Adler, M Pellauer, A Parashar
Leveraging latency-insensitivity to ease multiple FPGA design,” in FPGA, 175-184, 2012
52012
Sos: Using speculation for memory error detection
S Gurumurthi, A Parashar, A Sivasubramaniam
Proceedings of the Workshop on High Performance Computing Reliability Issues …, 2005
52005
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach
H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
32019
Executing distributed memory operations using processing elements connected by distributed channels
B Ahsan, MC Adler, NC Crago, JS Emer, A Jaleel, A Parashar, ...
US Patent App. 16/443,717, 2019
32019
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