| Memory cell comprising one MOS transistor with an isolated body having a reinforced memory effect R Ranica, A Villaret, P Mazoyer US Patent 7,541,636, 2009 | 163 | 2009 |
| A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories R Ranica, A Villaret, C Fenouillet-Beranger, P Malinge, P Mazoyer, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 132 | 2004 |
| Truly innovative 28nm FDSOI technology for automotive micro-controller applications embedding 16MB phase change memory F Arnaud, P Zuliani, JP Reynard, A Gandolfo, F Disegni, P Mattavelli, ... 2018 IEEE International Electron Devices Meeting (IEDM), 18.4. 1-18.4. 4, 2018 | 79 | 2018 |
| Highly performant double gate MOSFET realized with SON process S Harrison, P Coronel, F Leverd, R Cerutti, R Palla, D Delille, S Borel, ... IEEE International Electron Devices Meeting 2003, 18.6. 1-18.6. 4, 2003 | 66 | 2003 |
| 1T MEMS memory based on suspended gate MOSFET N Abele, A Villaret, A Gangadharaiah, C Gabioud, P Ancey, AM Ionescu 2006 International Electron devices meeting, 1-4, 2006 | 57 | 2006 |
| A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM R Ranica, A Villaret, P Malinge, P Mazoyer, D Lenoble, P Candelier, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 128-129, 2004 | 48 | 2004 |
| High density embedded PCM cell in 28nm FDSOI technology for automotive micro-controller applications F Arnaud, P Ferreira, F Piazza, A Gandolfo, P Zuliani, P Mattavelli, ... 2020 IEEE International Electron Devices Meeting (IEDM), 24.2. 1-24.2. 4, 2020 | 37 | 2020 |
| An 8 Mbit DRAM design using a 1 Tbulk cell P Malinge, P Candelier, F Jacquet, S Martin, R Ranica, A Villaret, ... Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 358-361, 2005 | 37 | 2005 |
| Integrated memory circuit for storing a binary datum in a memory cell P Mazoyer, A Villaret, T Skotnicki US Patent 7,042,039, 2006 | 32 | 2006 |
| A new 40-nm SONOS structure based on backside trapping for nanoscale memories R Ranica, A Villaret, P Mazoyer, S Monfray, D Chanemougame, ... IEEE transactions on nanotechnology 4 (5), 581-587, 2005 | 30 | 2005 |
| Vertical IMOS transistor having a PIN diode formed within C Charbuillet, T Skotnicki, A Villaret US Patent 7,608,867, 2009 | 19 | 2009 |
| Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications R Ranica, A Villaret, P Malinge, G Gasiot, P Mazoyer, P Roche, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 38-39, 2005 | 18 | 2005 |
| 28nm FDSOI technology sub-0.6 V SRAM Vmin assessment for ultra low voltage applications R Ranica, N Planes, V Huard, O Weber, D Noblet, D Croain, F Giner, ... 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 14 | 2016 |
| Memory cell comprising one MOS transistor with an isolated body having an improved read sensitivity A Villaret, P Mazoyer, R Ranica US Patent 7,709,875, 2010 | 14 | 2010 |
| Memory cell comprising one MOS transistor with an isolated body having a prolonged memory effect R Ranica, A Villaret, P Mazoyer US Patent App. 11/479,220, 2007 | 14 | 2007 |
| 18nm FDSOI technology platform embedding PCM & innovative continuous-active construct enhancing performance for leading-edge MCU applications D Min, J Park, O Weber, F Wacquant, A Villaret, E Vandenbossche, ... 2021 IEEE International Electron Devices Meeting (IEDM), 13.1. 1-13.1. 4, 2021 | 13 | 2021 |
| Inverse lithography technique for advanced CMOS nodes A Villaret, A Tritchkov, J Entradas, E Yesilada Optical Microlithography XXVI 8683, 97-108, 2013 | 10 | 2013 |
| Confined VLS growth and structural characterization of silicon nanoribbons A Lecestre, E Dubois, A Villaret, T Skotnicki, P Coronel, G Patriarche, ... Microelectronic engineering 87 (5-8), 1522-1526, 2010 | 10 | 2010 |
| Fabrication and room-temperature single-charging behavior of self-aligned single-dot memory devices X Tang, N Reckinger, V Bayot, C Krzeminski, E Dubois, A Villaret, ... IEEE transactions on nanotechnology 5 (6), 649-656, 2006 | 10 | 2006 |
| Integrated semiconductor DRAM-type memory device and corresponding fabrication process T Skotnicki, A Villaret US Patent 6,759,721, 2004 | 8 | 2004 |
