| Blueshift: Designing processors for timing speculation from the ground up. B Greskamp, L Wan, UR Karpuzcu, JJ Cook, J Torrellas, D Chen, C Zilles 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 127 | 2009 |
| Dynatune: Circuit-level optimization for timing speculation considering dynamic path behavior L Wan, D Chen Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 73 | 2009 |
| LOPASS: A low-power architectural synthesis system for FPGAs with interconnect estimation and optimization D Chen, J Cong, Y Fan, L Wan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (4), 564-577, 2009 | 59 | 2009 |
| CCP: Common case promotion for improved timing error resilience with energy efficiency L Wan, D Chen Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 15 | 2012 |
| Analysis of circuit dynamic behavior with timed ternary decision diagram L Wan, D Chen 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 516-523, 2010 | 14 | 2010 |
| Analysis of circuit dynamic behavior with timed ternary decision diagram L Wan, D Chen 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 516-523, 2010 | 14 | 2010 |
| Temperature aware statistical static timing analysis A Rogachev, L Wan, D Chen 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 103-110, 2011 | 10 | 2011 |
| A coarse-grained reconfigurable architecture with compilation for high performance L Wan, C Dong, D Chen International Journal of Reconfigurable Computing 2012, 3-3, 2012 | 6 | 2012 |
| Analysis of digital circuit dynamic behavior with timed ternary decision diagrams for better-than-worst-case design L Wan, D Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 5 | 2012 |
| A new coarse-grained reconfigurable architecture with fast data relay and its compilation flow LWCDD Chen | 4 | 2009 |
| A new coarse-grained reconfigurable architecture with fast data relay and its compilation flow LWCDD Chen | 4 | 2009 |
| C-mine: Data mining of logic common cases for improved timing error resilience with energy efficiency CH Lin, L Wan, D Chen ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (2 …, 2017 | 2 | 2017 |
| C-Mine: Data mining of logic common cases for low power synthesis of Better-Than-Worst-Case designs CH Lin, L Wan, D Chen Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 2 | 2014 |
| A novel method in design optimization of instruction decoder and micro-control unit for ILP DSPs LWL Wan, XXX Xu, JCJ Chen ASIC, 2003. Proceedings. 5th International Conference on 1, 417-423, 2003 | 2 | 2003 |
| Analysis and optimization of digital circuit dynamic behavior L Wan University of Illinois at Urbana-Champaign, 2012 | 1 | 2012 |
| Semi-automated Thermal Envelope Model Setup for Adaptive Model Predictive Control with Event-triggered System Identification L Wan, X Dai, T Welfonder, E Petrova, P Pauwels arXiv preprint arXiv:2307.00638, 2023 | | 2023 |
| 微处理器复杂流水线管理量化方法 万律， 李飞鸣， 陈进 小型微型计算机系统 25 (8), 1517-1521, 2004 | | 2004 |
| 软硬件联合仿真方法进行微处理器流水线管理优化设计 万律， 许新任， 杜德臣 微电子学与计算机 20 (10), 7-10, 2003 | | 2003 |
Josep TorrellasProfessor of Computer Science, University of Illinois Urbana-ChampaignDirección de correo verificada de illinois.edu
