| 6.2 A 60Gb/s PAM-4 ADC-DSP transceiver in 7nm CMOS with SNR-based adaptive power scaling achieving 6.9 pJ/b at 32dB loss MA LaCroix, H Wong, YH Liu, H Ho, S Lebedev, P Krotnev, DA Nicolescu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 114-116, 2019 | 59 | 2019 |
| A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization TSC Kao, FA Musa, AC Carusone IEEE Transactions on Circuits and Systems I: Regular Papers 57 (11), 2844-2857, 2010 | 56 | 2010 |
| 8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2 MA LaCroix, E Chong, W Shen, E Nir, FA Musa, H Mei, MM Mohsenpour, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 132-134, 2021 | 46 | 2021 |
| Modeling and design of multilevel bang–bang CDRs in the presence of ISI and noise FA Musa, AC Carusone IEEE Transactions on Circuits and Systems I: Regular Papers 54 (10), 2137-2147, 2007 | 37 | 2007 |
| A 32/16-Gb/s dual-mode pulsewidth modulation pre-emphasis (PWM-PE) transmitter with 30-dB loss compensation using a high-speed CML design methodology H Cheng, FA Musa, AC Carusone IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1794-1806, 2009 | 23 | 2009 |
| A baud-rate timing recovery scheme with a dual-function analog filter FA Musa, AC Carusone IEEE Transactions on Circuits and Systems II: Express Briefs 53 (12), 1393-1397, 2006 | 20 | 2006 |
| Clock recovery in high-speed multilevel serial links FA Musa, AC Carusone Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003 | 20 | 2003 |
| High-speed baud-rate clock and data recovery FA Musa, AC Carusone 2007 7th International Conference on ASIC, 64-69, 2007 | 9 | 2007 |
| A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET E Chong, FA Musa, AN Mustafa, T Gao, P Krotnev, R Soreefan, Q Xin, ... ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 8 | 2021 |
| Noise analysis of phase locked loops and system trade-offs FA Musa Department of Electrical and Computer Engineering, University of Toronto …, 2002 | 8 | 2002 |
| High-speed baud-rate clock recovery FA Musa University of Toronto, 2008 | 7 | 2008 |
| Normally-off GaN HEMT for high power and high-frequency applications AZ Musa, MM Isa, N Ahmad, S Taking, FA Musa AIP Conference Proceedings 2347 (1), 2021 | 4 | 2021 |
| 112G+ 7-bit DAC-based transmitter in 7-nm FinFET with PAM4/6/8 modulation E Chong, SN Shahi, FA Musa, AN Mustafa, P Krotnev, P Madeira, ... IEEE Solid-State Circuits Letters 5, 21-24, 2022 | 3 | 2022 |
| 56/28-Gb/s PAM4/PAM2 Impedance-Modulated Transmitter Enabling 44-dB/58-dB Loss Compensation at 14 GHz in a 7-nm FinFET Transceiver FA Musa, E Chong, D Tonietto IEEE Solid-State Circuits Letters 3, 242-245, 2020 | 1 | 2020 |
| Design and analysis of folded cascode operational amplifier using 0.13 µm CMOS technology NA Lee Cha Sing, MM Isa, FAS Musa AIP CONFERENCE PROCEEDINGS, 2020 | 1 | 2020 |
| Two-tap travelling-wave infinite impulse response filter with 12 dB peaking at 24 GHz G Ng, FA Musa, AC Carusone Electronics letters 45 (9), 463-464, 2009 | 1 | 2009 |
| A passive filter aided timing recovery scheme FA Musa, AC Carusone 2008 IEEE International Symposium on Circuits and Systems, 3065-3068, 2008 | 1 | 2008 |
| Method and Apparatus for Multi-Mode Multi-Level Transmitter FAM Euhan Chong US Patent 20,210,021,056, 2021 | | 2021 |
| Integrated Circuits for Dispersion Compensation in Optical Communication Links AC Carusone, FA Musa, J Sewter, G Ng Convergence of Mobile and Stationary Next‐Generation Networks, 675-706, 2010 | | 2010 |
| Design of a 4.0-4.4375 GHz Phase Locked Loop Based Frequency Synthesizer FA Musa University of Connecticut, 2001 | | 2001 |
Anthony Chan CarusoneProfessor of Electrical Engineering, University of TorontoDirección de correo verificada de isl.utoronto.ca
