Gustavo Sutter
TitleCited byYear
Synthesis of arithmetic circuits
JP Deschamps, GJA Bioul, GD Sutter
Wiley-Interscience, 2006
2542006
Hardware implementation of finite-field arithmetic
JP Deschamps
McGraw-Hill, Inc., 2009
1432009
Efficient elliptic curve point multiplication using digit-serial binary field operations
GD Sutter, JP Deschamps, JL Imaña
IEEE Transactions on Industrial Electronics 60 (1), 217-225, 2012
1132012
Modular multiplication and exponentiation architectures for fast RSA cryptosystem based on digit serial computation
GD Sutter, JP Deschamps, JL Imaña
IEEE Transactions on industrial electronics 58 (7), 3101-3109, 2010
702010
Low-power FSMs in FPGA: Encoding alternatives
G Sutter, E Todorovich, S López-Buedo, E Boemo
International Workshop on Power and Timing Modeling, Optimization and …, 2002
452002
Guide to FPGA implementation of arithmetic functions
JP Deschamps, GD Sutter, E Cantó
Springer Science & Business Media, 2012
392012
FPGA implementations of BCD multipliers
G Sutter, E Todorovich, G Bioul, M Vazquez, JP Deschamps
2009 International Conference on Reconfigurable Computing and FPGAs, 36-41, 2009
342009
Experiments in low power FPGA design
G Sutter, E Boemo
Latin American applied research 37 (1), 99-104, 2007
282007
FSM decomposition for low power in FPGA
G Sutter, E Todorovich, S Lopez-Buedo, E Boemo
International Conference on Field Programmable Logic and Applications, 350-359, 2002
252002
Decimal addition in FPGA
G Bioul, M Vazquez, JP Deschamps, G Sutter
2009 5th Southern Conference on Programmable Logic (SPL), 101-108, 2009
232009
Decimal adders/subtractors in FPGA: efficient 6-input LUT implementations
M Vazquez, G Sutter, G Bioul, JP Deschamps
2009 International Conference on Reconfigurable Computing and FPGAs, 42-47, 2009
202009
High speed fixed point dividers for FPGAs
G Sutter, JP Deschamps
2009 International Conference on Field Programmable Logic and Applications …, 2009
202009
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture
I Gonzalez, S Lopez-Buedo, G Sutter, D Sanchez-Roman, ...
Journal of Systems Architecture 58 (6-7), 247-256, 2012
192012
A tool for activity estimation in FPGAs
E Todorovich, M Gilabert, G Sutter, S López-Buedo, E Boemo
International Conference on Field Programmable Logic and Applications, 340-349, 2002
172002
Bridging the gap between hardware and software open source network developments
M Forconesi, G Sutter, S López-Buedo, JEL de Vergara, J Aracil
IEEE Network 28 (5), 13-19, 2014
162014
End-user low-power alternatives at topological and physical levels. Some examples on FPGAs
E Todorovich, G Sutter, N Acosta, E Boemo, S López-Buedo
Proc. DCIS'2000, 18-23, 2000
162000
Decimal division: Algorithms and FPGA implementations
JP Deschamps, G Sutter
2010 VI Southern Programmable Logic Conference (SPL), 67-72, 2010
152010
Power aware dividers in FPGA
G Sutter, JP Deschamps, G Bioul, E Boemo
International Workshop on Power and Timing Modeling, Optimization and …, 2004
132004
Comparative study of SRT-dividers in FPGA
G Sutter, G Bioul, JP Deschamps
International Conference on Field Programmable Logic and Applications, 209-220, 2004
132004
TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces
JF Zazo, M Forconesi, S Lopez-Buedo, G Sutter, J Aracil
2014 International Conference on ReConFigurable Computing and FPGAs …, 2014
122014
The system can't perform the operation now. Try again later.
Articles 1–20