Svilen Kanev
Svilen Kanev
Software Engineer, Google
Verified email at - Homepage
Cited by
Cited by
Profiling a warehouse-scale computer
S Kanev, JP Darago, K Hazelwood, P Ranganathan, T Moseley, GY Wei, ...
International Symposium on Computer Architecture (ISCA), 2015
Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling
VJ Reddi, S Kanev, W Kim, S Campanoni, MD Smith, GY Wei, D Brooks
Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium …, 2010
Tradeoffs between Power Management and Tail Latency in Warehouse-Scale Applications
S Kanev, K Hazelwood, GY Wei, D Brooks
IEEE International Symposium on Workload Characterization (IISWC), 2014
HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
S Campanoni, K Brownell, S Kanev, TM Jones, D Brooks, GY Wei
International Symposium on Computer Architecture (ISCA), 2014
Characterizing and evaluating voltage noise in multi-core near-threshold processors
X Zhang, T Tong, S Kanev, SK Lee, GY Wei, D Brooks
International Symposium on Low Power Electronics and Design (ISLPED), 82-87, 2013
Voltage Noise in Production Processors
VJ Reddi, S Kanev, W Kim, S Campanoni, MD Smith, GY Wei, D Brooks
IEEE Micro 31 (1), 20-28, 2011
Galaxy-scale Bars in Late-type Sloan Digital Sky Survey Galaxies Do Not Influence the Average Accretion Rates of Supermassive Black Holes
AD Goulding, E Matthaey, JE Greene, RC Hickox, DM Alexander, ...
The Astrophysical Journal 843 (2), 135, 2017
Mallacc: Accelerating memory allocation
S Kanev, SL Xi, GY Wei, D Brooks
International Conference on Architectural Support for Programming Languages …, 2017
XIOSim: power-performance modeling of mobile x86 cores
S Kanev, GY Wei, D Brooks
international symposium on Low power electronics and design (ISLPED), 267-272, 2012
Carb: A c-state power management arbiter for latency-critical workloads
X Zhan, R Azimi, S Kanev, D Brooks, S Reda
IEEE Computer Architecture Letters 16 (1), 6-9, 2016
Motivating software-driven current balancing in flexible voltage-stacked multicore processors
S Kanev
Harvard University Cambridge, Massachusetts, 2012
Portable trace compression through instruction interpretation
S Kanev, R Cohn
(IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011
Methods and apparatus for parallel processing
GY Wei, DM Brooks, S Campanoni, KM Brownell, S Kanev
US Patent App. 14/898,894, 2016
Measuring Code Optimization Impact on Voltage Noise
S Kanev, TM Jones, GY Wei, D Brooks, VJ Reddi
Workshop on Silicon Errors in Logic - System Effects (SELSE) 40, 2013
AsmDB: understanding and mitigating front-end stalls in warehouse-scale computers
G Ayers, NP Nagendra, DI August, HK Cho, S Kanev, C Kozyrakis, ...
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
Automatically accelerating non-numerical programs by architecture-compiler co-design
S Campanoni, K Brownell, S Kanev, TM Jones, GY Wei, D Brooks
Communications of the ACM 60 (12), 88-97, 2017
Breaking Cyclic-Multithreading Parallelization with XML Parsing
S Campanoni, S Kanev, K Brownell, GY Wei, D Brooks
Workshop on Parallelism in Mobile Platforms (PRISM), 2014
RoboCup Team Description Paper: RFC Cambridge
D Robinson, AC Walker Chan, K Haller, J Henion, B Johnson, S Kanev, ...
AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers
NP Nagendra, G Ayers, DI August, HK Cho, S Kanev, C Kozyrakis, ...
IEEE Micro 40 (3), 56-63, 2020
Efficiency in warehouse-scale computers: a datacenter tax study
S Kanev
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