| Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level J Patel, D Sharma, S Yadav, A Lemtur, P Suman Microelectronics Journal 85, 72-82, 2019 | 56 | 2019 |
| Performance analysis of gate all around GaAsP/AlGaSb CP-TFET A Lemtur, D Sharma, P Suman, J Patel, DS Yadav, N Sharma Superlattices and Microstructures 117, 364-372, 2018 | 16 | 2018 |
| Linearity and reliability analysis of an electrically doped hetero material nanowire TFET C Rajan, DP Samajdar, J Patel, A Lodhi, SK Agnihotri, D Sharma, ... Journal of Electronic Materials 49, 4307-4317, 2020 | 14 | 2020 |
| Implementation of∑ Δ ADC using electrically doped III‐V ternary alloy semiconductor nano‐wire TFET C Rajan, J Patel, D Sharma, AK Behera, A Lodhi, A Lemtur, DP Samajdar Micro & Nano Letters 15 (4), 266-271, 2020 | 13 | 2020 |
| Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications J Patel, S Banchhor, S Guglani, A Dasgupta, S Roy, A Bulusu, ... 2022 35th International Conference on VLSI Design and 2022 21st …, 2022 | 7 | 2022 |
| Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs S Guglani, J Patel, A Dasgupta, S Dasgupta, MY Kao, C Hu, S Roy 2022 Device Research Conference (DRC), 1-2, 2022 | 5 | 2022 |
| Two‐stage op‐amp and integrator realisation through GaAsP/AlGaSb nanowire CP‐TFET A Lemtur, D Sharma, J Patel, P Suman, C Rajan Micro & Nano Letters 14 (9), 980-985, 2019 | 5 | 2019 |
| Analytical Model of Center Potential in GaN Vertical Junctionless Power Fin-MOSFETs for Fast Device-Design Optimization J Patel, T Pramanik, B Sarkar IEEE Transactions on Electron Devices, 2023 | 3 | 2023 |
| Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor V Kumar, J Patel, A Datta, S Dasgupta Memories-Materials, Devices, Circuits and Systems 4, 100056, 2023 | 3 | 2023 |
| Performance Analysis of Sigma Delta ADC Developed using Electrically Doped GAPSb/InP Gate All Around Tunnel Field Effect Transistor AK Behera, C Rajan, DP Samajdar, A Lodhi, J Patel, K Mishra, DS Yadav Journal of Electronic Materials 50 (10), 5740-5753, 2021 | 2 | 2021 |
| Low Power Physical Layer Security Solutions for IoT Devices C Rajan, D Sharma, DP Samajdar, J Patel Recent Advances in Security, Privacy, and Trust for Internet of Things (IoT …, 2020 | 2 | 2020 |
| A novel proposal for enhancing tunnel field effect transistor performance and its reliability issues S Yadav, J Patel, D Sharma Journal of Nanoelectronics and Optoelectronics 14 (2), 238-246, 2019 | 2 | 2019 |
| A Novel NW-TFET Based Low Power, High Speed and Variations Resistant Comparator with Improved Linearity C Rajan, J Patel, VR Satpute, DP Samajdar 1st International Conference on the Paradigm Shifts in Communication …, 2022 | 1 | 2022 |
| Impact of Gate All Around Architecture in Polarity Based TFET with RF/Analog Analysis C Rajan, P Suman, B Neole, J Patel 2023 2nd International Conference on Paradigm Shifts in Communications …, 2023 | | 2023 |
| Small-Signal Model of Nanosheet FET for High-Frequency Range: A Design Perspective of Parallel Stacking and Dual-Dielectric Spacer J Patel, N Aggarwal, N Bagga, S Dasgupta 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023 | | 2023 |
| FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor V Kumar, J Patel, A Datta, S Dasgupta 2023 36th International Conference on VLSI Design and 2023 22nd …, 2023 | | 2023 |
| Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation J Patel, N Bagga, S Banchhor, S Dasgupta 2022 IEEE International Conference on Emerging Electronics (ICEE), 1-5, 2022 | | 2022 |
| FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet V Kumar, J Patel, A Datta, S Dasgupta International Symposium on VLSI Design and Test, 3-11, 2022 | | 2022 |
| Performance Booster Electrical Drain SiGe Nanowire TFET (EDD-SiGe-NW-TFET) with DC Analysis and Optimization J Patel, P Suman, A Lemtur, D Sharma Information and Communication Technology for Intelligent Systems …, 2019 | | 2019 |
| Significance of Hetero-Junction in Charge Plasma Gate All Around TFET: An Investigation A Lemtur, P Suman, J Patel, D Sharma Information and Communication Technology for Intelligent Systems …, 2018 | | 2018 |
Dr Dheeraj sharmaIndian Institute of Information Technology Design & Manufacturing JabalpurVerified email at iiitdmj.ac.in
