Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating M Cho, ST Kim, C Tokunaga, C Augustine, JP Kulkarni, K Ravichandran, ...
IEEE Journal of Solid-State Circuits 52 (1), 50-63, 2016
90 2016 Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system M Cho, C Liu, DH Kim, SK Lim, S Mukhopadhyay
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 694-697, 2010
78 2010 Pre-bond and post-bond test and signal recovery structure to characterize and repair TSV defect induced signal degradation in 3-D system M Cho, C Liu, DH Kim, SK Lim, S Mukhopadhyay
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 …, 2011
72 2011 Reconfigurable SRAM architecture with spatial voltage scaling for low power mobile multimedia applications M Cho, J Schlessman, W Wolf, S Mukhopadhyay
IEEE transactions on very large scale integration (VLSI) systems 19 (1), 161-165, 2009
54 2009 An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS P Meinerzhagen, C Tokunaga, A Malavasi, V Vaidya, A Mendon, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 38-40, 2018
33 2018 Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications M Cho, J Schlessman, W Wolf, S Mukhopadhyay
2009 Asia and South Pacific Design Automation Conference, 823-828, 2009
30 2009 Characterization of radiation-induced SRAM and logic soft errors from 0.33 V to 1.0 V in 65nm CMOS R Pawlowski, J Crop, M Cho, J Tschanz, V De, T Fairbanks, H Quinn, ...
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014
24 2014 Proactive power migration to reduce maximum value and spatiotemporal non-uniformity of on-chip temperature distribution in homogeneous many-core processors M Cho, N Sathe, M Gupta, S Kumar, S Yalamanchilli, S Mukhopadhyay
2010 26th Annual IEEE Semiconductor Thermal Measurement and Management …, 2010
24 2010 An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V} _ {\text {MIN}} $ Optimization PA Meinerzhagen, C Tokunaga, A Malavasi, V Vaidya, A Mendon, ...
IEEE Journal of Solid-State Circuits 54 (1), 144-157, 2018
23 2018 Thermal system identification (TSI): A methodology for post-silicon characterization and prediction of the transient thermal field in multicore chips M Cho, W Song, S Yalamanchili, S Mukhopadhyay
2012 28th Annual IEEE Semiconductor Thermal Measurement and Management …, 2012
17 2012 Characterization of inverse temperature dependence in logic circuits M Cho, M Khellah, K Chae, K Ahmed, J Tschanz, S Mukhopadhyay
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012
16 2012 Analysis of neutron-induced multibit-upset clusters in a 14-nm flip-flop array S Kumar, M Cho, L Everson, Q Tang, P Meinerzhagen, A Malavasi, ...
IEEE Transactions on Nuclear Science 66 (6), 918-925, 2019
13 2019 Thermal investigation into power multiplexing for homogeneous many-core processors M Prakash Gupta, M Cho, S Mukhopadhyay, S Kumar
12 2012 Power multiplexing for thermal field management in many-core processors M Cho, C Kersey, MP Gupta, N Sathe, S Kumar, S Yalamanchili, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (1 …, 2012
11 2012 Thermal mangament of multicore processors using power multiplexing MP Gupta, M Cho, S Mukhopadhyay, S Kumar
2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical …, 2010
11 2010 Impact of die-to-die thermal coupling on the electrical characteristics of 3D stacked SRAM cache S Chatterjee, M Cho, R Rao, S Mukhopadhyay
2012 28th Annual IEEE Semiconductor Thermal Measurement and Management …, 2012
10 2012 Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS M Cho, C Tokunaga, MM Khellah, JW Tschanz, V De
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015
9 2015 Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration M Cho, N Sathe, A Raychowdhury, S Mukhopadhyay
2010 IEEE International Test Conference, 1-9, 2010
8 2010 An All-Digital, -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop S Bang, M Cho, PA Meinerzhagen, A Malavasi, MM Khellah, JW Tschanz, ...
IEEE Journal of Solid-State Circuits 55 (7), 1898-1908, 2020
7 2020 Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique S Kumar, M Cho, L Eversen, H Kim, Q Tang, P Mazanec, P Meinerzhagen, ...
2017 Symposium on VLSI Circuits, C114-C115, 2017
7 2017