| A 24–72-GS/s 8-b time-interleaved SAR ADC with 2.0–3.3-pJ/conversion and> 30 dB SNDR at Nyquist in 14-nm CMOS FinFET L Kull, D Luu, C Menolfi, M Braendli, PA Francese, T Morf, M Kossel, ... IEEE Journal of Solid-State Circuits 53 (12), 3508-3516, 2018 | 126 | 2018 |
| 28.5 A 10b 1.5 GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET L Kull, D Luu, C Menolfi, M Braendli, PA Francese, T Morf, M Kossel, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 474-475, 2017 | 100 | 2017 |
| A 112Gb/S 2.6 pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS C Menolfi, M Braendli, PA Francese, T Morf, A Cevrero, M Kossel, L Kull, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 104-106, 2018 | 74 | 2018 |
| A 64-Gb/s 1.4-pJ/b NRZ optical receiver data-path in 14-nm CMOS FinFET I Ozkaya, A Cevrero, PA Francese, C Menolfi, T Morf, M Brändli, ... IEEE Journal of Solid-State Circuits 52 (12), 3458-3473, 2017 | 67 | 2017 |
| 6.1 A 100Gb/s 1.1 pJ/b PAM-4 RX with dual-mode 1-tap PAM-4/3-tap NRZ speculative DFE in 14nm CMOS FinFET A Cevrero, I Ozkaya, PA Francese, M Brandli, C Menolfi, T Morf, M Kossel, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 112-114, 2019 | 61 | 2019 |
| 29.1 A 64Gb/s 1.4 pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET A Cevrero, I Ozkaya, PA Francese, C Menolfi, T Morf, M Brandli, D Kuchta, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 482-483, 2017 | 46 | 2017 |
| A 161-mW 56-Gb/s ADC-based discrete multitone wireline receiver data-path in 14-nm FinFET G Kim, L Kull, D Luu, M Braendli, C Menolfi, PA Francese, H Yueksel, ... IEEE Journal of Solid-State Circuits 55 (1), 38-48, 2019 | 39 | 2019 |
| A 56Gb/s burst-mode NRZ optical receiver with 6.8 ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS I Ozkaya, A Cevrero, PA Francese, C Menolfi, M Braendli, T Morf, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 266-268, 2018 | 31 | 2018 |
| A 3.6 pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS H Yueksel, L Kull, A Burg, M Braendli, P Buchmann, PA Francese, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 30 | 2015 |
| A 12-bit 300-MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14-nm CMOS FinFET D Luu, L Kull, T Toifl, C Menolfi, M Brändli, PA Francese, T Morf, M Kossel, ... IEEE Journal of Solid-State Circuits 53 (11), 3268-3279, 2018 | 27 | 2018 |
| A 10-bit 20–40 GS/s ADC with 37 dB SNDR at 40 GHz input using first order sampling bandwidth calibration L Kull, D Luu, C Menolfi, T Morf, PA Francese, M Braendli, M Kossel, ... 2018 IEEE Symposium on VLSI Circuits, 275-276, 2018 | 23 | 2018 |
| A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET D Luu, L Kull, T Toifl, C Menolfi, M Braendli, PA Francese, T Morf, ... 2017 Symposium on VLSI Circuits, C276-C277, 2017 | 15 | 2017 |
| CMOS ADCs towards 100 GS/s and beyond L Kull, D Luu, PA Francese, C Menolfi, M Braendli, M Kossel, T Morf, ... 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 1-4, 2016 | 14 | 2016 |
| A 60-Gb/s 1.9-pJ/bit NRZ optical receiver with low-latency digital CDR in 14-nm CMOS FinFET I Ozkaya, A Cevrero, PA Francese, C Menolfi, T Morf, M Brändli, ... IEEE Journal of Solid-State Circuits 53 (4), 1227-1237, 2018 | 13 | 2018 |
| A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET A Cevrero, I Ozkaya, PA Francese, C Menolfi, M Braendli, T Morf, ... 2017 Symposium on VLSI Circuits, C320-C321, 2017 | 12 | 2017 |
| Design techniques for high-speed multi-level Viterbi detectors and trellis-coded-modulation decoders H Yueksel, M Braendli, A Burg, G Cherubini, RD Cideciyan, PA Francese, ... IEEE Transactions on Circuits and Systems I: Regular Papers 65 (10), 3529-3542, 2018 | 11 | 2018 |
| 23.6 A 30Gb/s 0.8 pJ/b 14nm FinFET receiver data-path PA Francese, M Brändli, C Menolfi, M Kossel, T Morf, L Kull, A Cevrero, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 408-409, 2016 | 10 | 2016 |
| A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS H Yueksel, M Braendli, A Burg, G Cherubini, RD Cideciyan, PA Francese, ... ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 309-312, 2016 | 9 | 2016 |
| 10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver PA Francese, T Toifl, M Braendli, C Menolfi, M Kossel, T Morf, L Kull, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 8 | 2015 |
| A 50GB/S 1.6 PJ/B RX data-path with quarter-rate 3-tap speculative DFE PA Francese, A Cevrero, I Ozkaya, M Brandli, C Menolfi, T Morf, M Kossel, ... 2018 IEEE Symposium on VLSI Circuits, 267-268, 2018 | 7 | 2018 |
