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Mark Ferriss
Mark Ferriss
Nubis communications
Verified email at nubis-communications.com
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Year
A 28-GHz 32-element TRX phased-array IC with concurrent dual-polarized operation and orthogonal phase and gain control for 5G communications
B Sadhu, Y Tousi, J Hallin, S Sahl, SK Reynolds, Ö Renström, K Sjögren, ...
IEEE Journal of Solid-State Circuits 52 (12), 3373-3391, 2017
3332017
A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback
D Dalton, K Chai, E Evans, M Ferriss, D Hitchcox, P Murray, ...
IEEE Journal of Solid-State Circuits 40 (12), 2713-2725, 2005
1252005
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, JO Plouchart, AV Rylyakov, ...
IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013
962013
A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS
A Valdes-Garcia, A Natarajan, D Liu, M Sanduleanu, X Gu, M Ferriss, ...
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 375-378, 2013
732013
A 28 ghz hybrid pll in 32 nm soi cmos
M Ferriss, A Rylyakov, JA Tierno, H Ainspan, DJ Friedman
IEEE Journal of Solid-State Circuits 49 (4), 1027-1035, 2014
602014
A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme
MA Ferriss, MP Flynn
IEEE Journal of Solid-State Circuits 43 (11), 2464-2471, 2008
522008
An integral path self-calibration scheme for a dual-loop PLL
M Ferriss, JO Plouchart, A Natarajan, A Rylyakov, B Parker, JA Tierno, ...
IEEE Journal of Solid-State Circuits 48 (4), 996-1008, 2013
402013
A 1.4 pJ/bit, power-scalable 16× 12 Gb/s source-synchronous I/O with DFE receiver in 32 nm SOI CMOS technology
TO Dickson, Y Liu, SV Rylov, A Agrawal, S Kim, PH Hsieh, JF Bulzacchelli, ...
IEEE Journal of Solid-State Circuits 50 (8), 1917-1931, 2015
392015
A 14mW fractional-N PLL modulator with an enhanced digital phase detector and frequency switching scheme
M Ferriss, MP Flynn
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
362007
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme
M Ferriss, B Sadhu, A Rylyakov, H Ainspan, D Friedman
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
332015
A 52 GHz frequency synthesizer featuring a 2nd harmonic extraction technique that preserves VCO performance
B Sadhu, M Ferriss, A Valdes-Garcia
IEEE Journal of Solid-State Circuits 50 (5), 1214-1223, 2015
312015
A 73.9–83.5 GHz synthesizer with− 111dBc/Hz phase noise at 10MHz offset in a 130nm SiGe BiCMOS technology
JO Plouchart, M Ferriss, B Sadhu, M Sanduleanu, B Parker, S Reynolds
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 123-126, 2013
312013
Indirect performance sensing for on-chip self-healing of analog and RF circuits
S Sun, F Wang, S Yaldiz, X Li, L Pileggi, A Natarajan, M Ferriss, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2243-2252, 2014
282014
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
S Sun, F Wang, S Yaldiz, X Li, L Pileggi, A Natarajan, M Ferriss, ...
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013
232013
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
JO Plouchart, MA Ferriss, AS Natarajan, A Valdes-Garcia, B Sadhu, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (8), 2009-2017, 2013
212013
A capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer
B Sadhu, M Ferriss, D Friedman
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 111-114, 2015
192015
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
M Ferriss, B Sadhu, A Rylyakov, H Ainspan, D Friedman
2016 IEEE International Solid-State Circuits Conference (ISSCC), 196-198, 2016
182016
A 250-mW 60-GHz CMOS transceiver SoC integrated with a four-element AiP providing broad angular link coverage
B Sadhu, A Valdes-Garcia, JO Plouchart, H Ainspan, AK Gupta, M Ferriss, ...
IEEE Journal of Solid-State Circuits 55 (6), 1516-1529, 2019
162019
A 21.8–27.5 GHz PLL in 32nm SOI using Gm linearization to achieve− 130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
B Sadhu, MA Ferriss, JO Plouchart, AS Natarajan, AV Rylyakov, ...
2012 IEEE Radio Frequency Integrated Circuits Symposium, 75-78, 2012
162012
Scalable polarimetric phased array transceiver
HA Ainspan, M Ferriss, AS Natarajan, BD Parker, JO Plouchart, ...
US Patent 10,416,283, 2019
142019
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