Hyesoon Kim
Hyesoon Kim
Verified email at cc.gatech.edu
TitleCited byYear
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
S Hong, H Kim
ACM SIGARCH Computer Architecture News 37 (3), 152-163, 2009
6832009
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping
CK Luk, S Hong, H Kim
2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture …, 2009
6012009
An integrated GPU power and performance model
S Hong, H Kim
ACM SIGARCH Computer Architecture News 38 (3), 280-289, 2010
5252010
Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers
S Srinath, O Mutlu, H Kim, YN Patt
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
3192007
A performance analysis framework for identifying potential benefits in GPGPU applications
J Sim, A Dasgupta, H Kim, R Vuduc
ACM SIGPLAN Notices 47 (8), 11-22, 2012
1872012
Many-thread aware prefetching mechanisms for GPGPU applications
J Lee, NB Lakshminarayana, H Kim, R Vuduc
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 213-224, 2010
1362010
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
J Lee, H Kim
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
1302012
When prefetching works, when it doesn’t, and why
J Lee, H Kim, R Vuduc
ACM Transactions on Architecture and Code Optimization (TACO) 9 (1), 2, 2012
1162012
SD3: A scalable approach to dynamic data-dependence profiling
M Kim, H Kim, CK Luk
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 535-546, 2010
1082010
A mostly-clean DRAM cache for effective hit speculation and self-balancing dispatch
J Sim, GH Loh, H Kim, M OConnor, M Thottethodi
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 247-257, 2012
922012
Techniques for efficient processing in runahead execution engines
O Mutlu, H Kim, YN Patt
ACM SIGARCH Computer Architecture News 33 (2), 370-381, 2005
892005
Age based scheduling for asymmetric multiprocessors
NB Lakshminarayana, J Lee, H Kim
Proceedings of the conference on high performance computing networking …, 2009
862009
GraphBIG: understanding graph computing in the context of industrial solutions
L Nai, Y Xia, IG Tanase, H Kim, CY Lin
SC'15: Proceedings of the International Conference for High Performance …, 2015
852015
Graphpim: Enabling instruction-level pim offloading in graph computing frameworks
L Nai, R Hadidi, J Sim, H Kim, P Kumar, H Kim
2017 IEEE International symposium on high performance computer architecture …, 2017
782017
Transparent hardware management of stacked dram as part of memory
J Sim, AR Alameldeen, Z Chishti, C Wilkerson, H Kim
Proceedings of the 47th Annual IEEE/ACM International Symposium on …, 2014
712014
Efficient runahead execution: Power-efficient memory latency tolerance
O Mutlu, H Kim, YN Patt
IEEE Micro 26 (1), 10-20, 2006
672006
Wish branches: Combining conditional branching and predication for adaptive predicated execution
H Kim, O Mutlu, J Stark, YN Patt
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005
582005
Effect of instruction fetch and memory scheduling on gpu performance
NB Lakshminarayana, H Kim
Workshop on Language, Compiler, and Architecture Support for GPGPU 88, 2010
572010
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
H Kim, JA Joao, O Mutlu, CJ Lee, YN Patt, R Cohn
ACM SIGARCH Computer Architecture News 35 (2), 424-435, 2007
532007
Address-value delta (AVD) prediction: Increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns
O Mutlu, H Kim, YN Patt
Proceedings of the 38th annual IEEE/ACM International Symposium on …, 2005
512005
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Articles 1–20