| Design methodology for IC manufacturability based on regular logic-bricks V Kheterpal, V Rovner, TG Hersan, D Motiani, Y Takegawa, AJ Strojwas, ... Proceedings of the 42nd annual Design Automation Conference, 353-358, 2005 | 136 | 2005 |
| Maximization of layout printability/manufacturability by extreme layout regularity T Jhaveri, V Rovner, L Pileggi, AJ Strojwas, D Motiani, V Kheterpal, ... Journal of Micro/Nanolithography, MEMS and MOEMS 6 (3), 031011-031011-15, 2007 | 77 | 2007 |
| Robot MP Michalowski, GR Katz, TG Hersan, AC Teeters US Patent 9,358,475, 2016 | 14 | 2016 |
| Robot MP Michalowski, GR Katz, TG Hersan US Patent 9,421,688, 2016 | 8 | 2016 |
| Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns MD Moe, LT Pileggi, VV Rovner, T Hersan, D Motiani, V Kheterpal US Patent App. 12/938,226, 2011 | 4 | 2011 |
| Systems and methods for calibrating light sources J Linnell, M Michalowski, JF Dupuis, T Hersan US Patent 9,157,795, 2015 | 2 | 2015 |
| Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns MD Moe, LT Pileggi, VV Rovner, T Hersan, D Motiani, V Kheterpal US Patent 7,827,516, 2010 | 1 | 2010 |
| Toy MP Michalowski, GR Katz, TG Hersan US Patent App. 29/473,694, 2014 | | 2014 |
