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Robot MP Michalowski, GR Katz, TG Hersan, AC Teeters US Patent 9,358,475, 2016 | 14 | 2016 |
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Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns MD Moe, LT Pileggi, VV Rovner, T Hersan, D Motiani, V Kheterpal US Patent 7,827,516, 2010 | 1 | 2010 |
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