| Dynamically controlled resource allocation in SMT processors FJ Cazorla, A Ramirez, M Valero, E Fernández 37th International Symposium on Microarchitecture (MICRO-37'04), 171-182, 2004 | 233 | 2004 |
| Enabling preemptive multiprogramming on GPUs I Tanasic, I Gelado, J Cabezas, A Ramirez, N Navarro, M Valero ACM SIGARCH Computer Architecture News 42 (3), 193-204, 2014 | 207 | 2014 |
| Supercomputing with commodity CPUs: Are mobile SoCs ready for HPC? N Rajovic, PM Carpenter, I Gelado, N Puzovic, A Ramirez, M Valero Proceedings of the International Conference on High Performance Computing …, 2013 | 199 | 2013 |
| Task superscalar: An out-of-order task pipeline Y Etsion, F Cabarcas, A Rico, A Ramirez, RM Badia, E Ayguade, ... 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 89-100, 2010 | 153 | 2010 |
| Tibidabo: Making the case for an ARM-based HPC system N Rajovic, A Rico, N Puzovic, C Adeniyi-Jones, A Ramirez Future Generation Computer Systems 36, 322-334, 2014 | 152 | 2014 |
| Multicore resource management KJ Nesbit, M Moreto, FJ Cazorla, A Ramirez, M Valero, JE Smith IEEE micro 28 (3), 6-16, 2008 | 137 | 2008 |
| Didi: Mitigating the performance impact of tlb shootdowns using a shared tlb directory C Villavieja, V Karakostas, L Vilanova, Y Etsion, A Ramirez, A Mendelson, ... 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 122 | 2011 |
| Parallel scalability of video decoders C Meenderinck, A Azevedo, B Juurlink, MA Mesa, A Ramirez Journal of Signal Processing Systems 57 (2), 173-194, 2009 | 121 | 2009 |
| Predictable performance in SMT processors: Synergy between the OS and SMTs FJ Cazorla, PMW Knijnenburg, R Sakellariou, E Fernandez, A Ramirez, ... IEEE Transactions on Computers 55 (7), 785-799, 2006 | 117 | 2006 |
| The low power architecture approach towards exascale computing N Rajovic, L Vilanova, C Villavieja, N Puzovic, A Ramirez Journal of Computational Science 4 (6), 439-443, 2013 | 106 | 2013 |
| Trace-driven simulation of multithreaded applications A Rico, A Duran, F Cabarcas, Y Etsion, A Ramirez, M Valero (IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011 | 98 | 2011 |
| A performance characterization of high definition digital video decoding using H. 264/AVC M Alvarez, E Salami, A Ramirez, M Valero IEEE International. 2005 Proceedings of the IEEE Workload Characterization …, 2005 | 89 | 2005 |
| Software trace cache A Ramirez, JL Larriba-Pey, C Navarro, J Torrellas, M Valero Proceedings of the 13th international conference on Supercomputing, 119-126, 1999 | 89 | 1999 |
| Code layout optimizations for transaction processing workloads A Ramirez, LA Barroso, K Gharachorloo, R Cohn, J Larriba-Pey, ... ACM SIGARCH Computer Architecture News 29 (2), 155-164, 2001 | 88 | 2001 |
| The Mont-Blanc prototype: an alternative approach for HPC systems N Rajovic, A Rico, F Mantovani, D Ruiz, JO Vilarrubi, C Gomez, L Backes, ... SC'16: Proceedings of the International Conference for High Performance …, 2016 | 81 | 2016 |
| Predictable performance in SMT processors FJ Cazorla, PMW Knijnenburg, R Sakellariou, E Fernández, A Ramirez, ... Proceedings of the 1st Conference on Computing Frontiers, 433-443, 2004 | 80 | 2004 |
| Fetching instruction streams A Ramirez, OJ Santana, JL Larriba-Pey, M Valero 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 77 | 2002 |
| Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster D Göddeke, D Komatitsch, M Geveler, D Ribbrock, N Rajovic, N Puzovic, ... Journal of Computational Physics 237, 132-150, 2013 | 74 | 2013 |
| Parallel H. 264 decoding on an embedded multicore processor A Azevedo, C Meenderinck, B Juurlink, A Terechko, J Hoogerbrugge, ... International Conference on High-Performance Embedded Architectures and …, 2009 | 74 | 2009 |
| High-performance embedded architecture and compilation roadmap K De Bosschere, W Luk, X Martorell, N Navarro, M O’Boyle, ... Transactions on High-Performance Embedded Architectures and Compilers I, 5-29, 2007 | 74 | 2007 |
Mateo ValeroProfessor and director of the Barcelona Supercomputing CenterVerified email at bsc.es
