Dr. Karthik Ganesan
Cited by
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Synthesizing memory-level parallelism aware miniature clones for spec cpu2006 and implantbench workloads
K Ganesan, J Jo, LK John
2010 IEEE International Symposium on Performance Analysis of Systems …, 2010
System-level Max Power (SYMPO)-A systematic approach for escalating system-level power consumption using synthetic benchmarks
K Ganesan, J Jo, WL Bircher, D Kaseridis, Z Yu, LK John
2010 19th International Conference on Parallel Architectures and Compilation …, 2010
MAximum Multicore POwer (MAMPO) an automatic multithreaded synthetic power virus generation framework for multicore systems
K Ganesan, LK John
Proceedings of 2011 International Conference for High Performance Computing …, 2011
Next-generation performance counters: Towards monitoring over thousand concurrent events
V Salapura, K Ganesan, A Gara, M Gschwind, JC Sexton, RE Walkup
ISPASS 2008-IEEE International Symposium on Performance Analysis of Systems …, 2008
Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design Multicore Processors
K Ganesan, LK John
IEEE Transactions on Computers, 2013
Generation, validation and analysis of SPEC CPU2006 simulation points based on branch, memory and TLB characteristics
K Ganesan, D Panwar, LK John
SPEC Benchmark Workshop, 121-137, 2009
A performance counter based workload characterization on Blue Gene/P
K Ganesan, L John, V Salapura, J Sexton
2008 37th International Conference on Parallel Processing, 330-337, 2008
The EH model: Analytical exploration of energy-harvesting architectures
J San Miguel, K Ganesan, M Badr, NE Jerger
IEEE Computer Architecture Letters 17 (1), 76-79, 2017
The What's Next Intermittent Computing Architecture
K Ganesan, J San Miguel, NE Jerger
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system
N Venkateswaran, VK Elangovan, K Ganesan, TPRS Sagar, ...
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-8, 2008
i-mirror: A software managed die-stacked dram-based memory subsystem
JH Ryoo, K Ganesan, YM Chen, LK John
2015 27th International Symposium on Computer Architecture and High …, 2015
The EH model: early design space exploration of intermittent processor architectures
J San Miguel, K Ganesan, M Badr, C Xia, R Li, H Hsiao, NE Jerger
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Methods to utilize heterogeneous memories with variable properties
L John, JH Ryoo, H Hsu, K Ganesan
US Patent App. 15/853,665, 2018
Scaling the Java Virtual Machine on a Many-Core System
K Ganesan, YM Chen, X Pan
Emerging Technology and Architecture for Big-data Analytics, 3-24, 2017
Low latency, high bandwidth memory subsystem incorporating die-stacked DRAM
JH Ryoo, K Ganesan, Y Chen
US Patent 9,406,361, 2016
Workload Synthesis for a Communications SoC
L John, J Jo, K Ganesan
Workshop on SoC Architecture, Accelerators and Workloads held in conjunction …, 2011
Hierarchical Multihost based operating System for simultaneous Multiple application Execution on MIP SCOC Cluster
K Ganesan
A Thesis Submitted to Waran Research Foundation 2006, 2006
Future generation supercomputers II: a paradigm for cluster architecture
N Venkateswaran, D Srinivasan, M Manivannan, TPR Sai Sagar, ...
ACM SIGARCH Computer Architecture News 35 (5), 61-70, 2007
Resource efficient acceleration of datastream analytics processing using an analytics accelerator
K Ganesan, SB Joshi, YM Chen, W Luyang, A Khawaja
US Patent 10,853,125, 2020
Clinical application of a novel next generation sequencing assay for CYP21A2 gene in 310 cases of 21-hydroxylase congenital adrenal hyperplasia from India
P Gangodkar, V Khadilkar, P Raghupathy, R Kumar, AA Dayal, D Dayal, ...
Endocrine, 1-10, 2020
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