A CMOS silicon spin qubit R Maurand, X Jehl, D Kotekar-Patil, A Corna, H Bohuslavskyi, R Laviéville, ...
Nature communications 7 (1), 13575, 2016
595 2016 Engineered substrates for future More Moore and More than Moore integrated devices L Clavelier, C Deguet, L Di Cioccio, E Augendre, A Brugere, P Gueguen, ...
2010 International Electron Devices Meeting, 2.6. 1-2.6. 4, 2010
250 2010 Germanium on Insulator and new 3D architectures opportunities for integration M Vinet, C Le Royer, P Batude, JF Damlencourt, JM Hartmann, L Hutin, ...
International Journal of Nanotechnology 7 (4-8), 304-319, 2010
194 2010 3DVLSI with CoolCube process: An alternative path to scaling P Batude, C Fenouillet-Beranger, L Pasini, V Lu, F Deprat, L Brunet, ...
2015 Symposium on VLSI Technology (VLSI Technology), T48-T49, 2015
151 2015 Gate-reflectometry dispersive readout and coherent control of a spin qubit in silicon A Crippa, R Ezzouch, A Aprá, A Amisse, R Lavieville, L Hutin, B Bertrand, ...
Nature communications 10 (1), 2776, 2019
142 2019 Gate-based high fidelity spin readout in a CMOS device M Urdampilleta, DJ Niegemann, E Chanrion, B Jadot, C Spence, ...
Nature nanotechnology 14 (8), 737-741, 2019
137 2019 Electrical Spin Driving by A Crippa, R Maurand, L Bourdet, D Kotekar-Patil, A Amisse, X Jehl, ...
Physical review letters 120 (13), 137702, 2018
134 2018 GeOI pMOSFETs scaled down to 30-nm gate length with record off-state current L Hutin, C Le Royer, JF Damlencourt, JM Hartmann, H Grampeix, ...
IEEE Electron Device Letters 31 (3), 234-236, 2010
134 2010 Cryogenic subthreshold swing saturation in FD-SOI MOSFETs described with band broadening H Bohuslavskyi, AGM Jansen, S Barraud, V Barral, M Cassé, L Le Guevel, ...
IEEE Electron Device Letters 40 (5), 784-787, 2019
111 2019 Electrically driven electron spin resonance mediated by spin–valley–orbit coupling in a silicon quantum dot A Corna, L Bourdet, R Maurand, A Crippa, D Kotekar-Patil, ...
npj quantum information 4 (1), 6, 2018
106 2018 Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures A Beckers, F Jazaeri, H Bohuslavskyi, L Hutin, S De Franceschi, C Enz
Solid-State Electronics 159, 106-115, 2019
95 2019 3D Sequential Integration: Application-driven technological achievements and guidelines P Batude, L Brunet, C Fenouillet-Beranger, F Andrieu, JP Colinge, ...
2017 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2017
90 2017 Characterization of contact resistance stability in MEM relays with tungsten electrodes Y Chen, R Nathanael, J Jeon, J Yaung, L Hutin, TJK Liu
Journal of Microelectromechanical Systems 21 (3), 511-513, 2012
73 2012 Fast gate-based readout of silicon quantum dots using Josephson parametric amplification S Schaal, I Ahmed, JA Haigh, L Hutin, B Bertrand, S Barraud, M Vinet, ...
Physical review letters 124 (6), 067701, 2020
69 2020 Single-electron operations in a foundry-fabricated array of quantum dots F Ansaloni, A Chatterjee, H Bohuslavskyi, B Bertrand, L Hutin, M Vinet, ...
Nature communications 11 (1), 6399, 2020
68 2020 Charge detection in an array of CMOS quantum dots E Chanrion, DJ Niegemann, B Bertrand, C Spence, B Jadot, J Li, ...
Physical Review Applied 14 (2), 024066, 2020
63 2020 A single hole spin with enhanced coherence in natural silicon N Piot, B Brun, V Schmitt, S Zihlmann, VP Michal, A Apra, ...
Nature Nanotechnology 17 (10), 1072-1077, 2022
62 2022 Spin readout of a CMOS quantum dot by gate reflectometry and spin-dependent tunneling VN Ciriano-Tejel, MA Fogarty, S Schaal, L Hutin, B Bertrand, L Ibberson, ...
PRX Quantum 2 (1), 010353, 2021
58 2021 High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate K Romanjek, L Hutin, C Le Royer, A Pouydebasque, MA Jaud, C Tabone, ...
Solid-state electronics 53 (7), 723-729, 2009
58 2009 Hybrid CMOS/BEOL-NEMS technology for ultra-low-power IC applications N Xu, J Sun, IR Chen, L Hutin, Y Chen, J Fujiki, C Qian, TJK Liu
2014 IEEE International Electron Devices Meeting, 28.8. 1-28.8. 4, 2014
56 2014 