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Pedro Benedicte
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Modelling the confidence of timing analysis for time randomised caches
P Benedicte, L Kosmidis, E Quiñones, J Abella, FJ Cazorla
2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), 2016
132016
Performance analysis and optimization of automotive gpus
F Mazzocchetti, P Benedicte, H Tabani, L Kosmidis, J Abella, FJ Cazorla
2019 31st International Symposium on Computer Architecture and High …, 2019
82019
RPR: A random replacement policy with limited pathological replacements
P Benedicte, C Hernandez, J Abella, FJ Cazorla
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 593-600, 2018
82018
A confidence assessment of WCET estimates for software time randomized caches
P Benedicte, L Kosmidis, E Quinones, J Abella, FJ Cazorla
2016 IEEE 14th International Conference on Industrial Informatics (INDIN), 90-97, 2016
72016
Performance analysis and optimization opportunities for Nvidia automotive GPUS
H Tabani, F Mazzocchetti, P Benedicte, J Abella, FJ Cazorla
Journal of Parallel and Distributed Computing 152, 21-32, 2021
62021
HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems
P Benedicte, C Hernandez, J Abella, FJ Cazorla
30th Euromicro Conference on Real-Time Systems (ECRTS 2018), 2018
62018
SafeTI: a hardware traffic injector for MPSoC functional and timing validation
O Sala, S Alcaide, G Cabo, F Bas, R Lorenzo, P Benedicte, D Trilla, G Gil, ...
2021 IEEE 27th international symposium on on-line testing and robust system …, 2021
52021
Design and integration of hierarchical-placement multi-level caches for real-time systems
P Benedicte, C Hernandez, J Abella, FJ Cazorla
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 455-460, 2018
52018
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
P Benedicte, C Hernandez, J Abella, FJ Cazorla
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 818-823, 2019
42019
SafeDM: a hardware diversity monitor for redundant execution on non-lockstepped cores
F Bas, P Benedicte, S Alcaide, G Cabo, F Mazzocchetti, J Abella
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 358-363, 2022
32022
SafeSoftDR: a library to enable software-based diverse redundancy for safety-critical tasks
F Mazzocchetti, S Alcaide, F Bas, P Benedicte, G Cabo, F Chang, ...
arXiv preprint arXiv:2210.00833, 2022
22022
SafeSU-2: a safe statistics unit for space MPSoCs
G Cabo, S Alcaide, C Hernández, P Benedicte, F Bas, F Mazzocchetti, ...
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
22022
Locality-aware cache random replacement policies
P Benedicte, C Hernandez, J Abella, FJ Cazorla
Journal of Systems Architecture 93, 48-61, 2019
22019
Towards limiting the impact of timing anomalies in complex real-time processors
P Benedicte, J Abella, C Hernandez, E Mezzetti, FJ Cazorla
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
22019
SafeDE: A Low-Cost Hardware Solution to Enforce Diverse Redundancy in Multicores
F Bas, S Alcaide, G Cabo, P Benedicte, J Abella
IEEE Transactions on Device and Materials Reliability 22 (2), 111-119, 2022
12022
Modeling contention interference in crossbar-based systems via sequence-aware pairing (SeAP)
J Giesen, P Benedicte, E Mezzetti, J Abella, FJ Cazorla
2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2020
12020
End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform
P Andreu, C Hernandez, T Picornell, P Lopez, S Alcaide, F Bas, ...
arXiv preprint arXiv:2210.04683, 2022
2022
Unboxing the Sand: on Deploying Safety Measures in the Programmable Logic of COTS MPSoCs
S Alcaide, G Cabo, F Bas, P Benedicte, F Mazzocchetti, F Cazorla, ...
11th European Congress Embedded Real Time Systems (ERTS 2022), 2022
2022
Smart hardware designs for probabilistically-analyzable processor architectures
P Benedicte Illescas
Universitat Politècnica de Catalunya, 2022
2022
De-RISC: a complete RISC-V based space-grade platform
NJ Wessman, F Malatesta, S Ribes, J Andersson, A García-Vilanova, ...
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 802-807, 2022
2022
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