Pedro Benedicte
Title
Cited by
Cited by
Year
Modelling the confidence of timing analysis for time randomised caches
P Benedicte, L Kosmidis, E Quiñones, J Abella, FJ Cazorla
2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), 2016
82016
A confidence assessment of WCET estimates for software time randomized caches
P Benedicte, L Kosmidis, E Quinones, J Abella, FJ Cazorla
2016 IEEE 14th International Conference on Industrial Informatics (INDIN), 90-97, 2016
62016
RPR: a random replacement policy with limited pathological replacements
P Benedicte, C Hernandez, J Abella, FJ Cazorla
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 593-600, 2018
52018
Performance analysis and optimization of automotive gpus
F Mazzocchetti, P Benedicte, H Tabani, L Kosmidis, J Abella, FJ Cazorla
2019 31st International Symposium on Computer Architecture and High …, 2019
32019
Design and integration of hierarchical-placement multi-level caches for real-time systems
P Benedicte, C Hernandez, J Abella, FJ Cazorla
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 455-460, 2018
32018
Towards limiting the impact of timing anomalies in complex real-time processors
P Benedicte, J Abella, C Hernandez, E Mezzetti, FJ Cazorla
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
12019
HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems
P Benedicte, C Hernandez, J Abella, FJ Cazorla
30th Euromicro Conference on Real-Time Systems (ECRTS 2018), 2018
12018
Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP)
J Giesen, P Benedicte, E Mezzetti, J Abella, FJ Cazorla
2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2020
2020
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
P Benedicte, C Hernandez, J Abella, FJ Cazorla
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 818-823, 2019
2019
Locality-aware cache random replacement policies
P Benedicte, C Hernandez, J Abella, FJ Cazorla
Journal of Systems Architecture 93, 48-61, 2019
2019
Improving Time-Randomized Cache Design
P Benedicte, C Hernández, J Abella, FJ Cazorla
Book of abstracts, 64-65, 2018
2018
On the analysis of the timing behaviour of time randomised caches
P Benedicte
Universitat Politècnica de Catalunya, 2016
2016
Towards limiting the impact of timing anomalies in complex real-time processors
P Benedicte Illescas, J Abella Ferrer, CE Hernández Chulde, E Mezzetti, ...
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