Juan Núñez-Martínez
Juan Núñez-Martínez
Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / Universidad de Sevilla)
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Cited by
Cited by
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
A Todri-Sanial, S Carapezzi, C Delacour, M Abernot, T Gil, E Corti, ...
IEEE Transactions on Neural Networks and Learning Systems 33 (5), 1996 - 2009, 2022
Efficient realisation of MOS-NDR threshold logic gates
J Núñez, MJ Avedillo, JM Quintana
Electronics letters 45 (23), 1, 2009
Comparison of TFETs and CMOS using optimal design points for power–speed tradeoffs
J Núñez, MJ Avedillo
IEEE Transactions on Nanotechnology 16 (1), 83-89, 2016
Operation limits for RTD-based MOBILE circuits
JM Quintana, MJ Avedillo, J Nunez, HP Roldán
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (2), 350-363, 2008
Digital implementation of oscillatory neural network for image recognition applications
M Abernot, T Gil, M Jiménez, J Núñez, MJ Avellido, B Linares-Barranco, ...
Frontiers in Neuroscience 15, 713054, 2021
Comparative analysis of projected tunnel and CMOS transistors for different logic application areas
J Nunez, MJ Avedillo
IEEE Transactions on Electron Devices 63 (12), 5012-5020, 2016
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J Núñez, MJ Avedillo, JM Quintana
Insights into the operation of hyper-FET-based circuits
MJ Avedillo, J Núñez
IEEE Transactions on Electron Devices 64 (9), 3912-3918, 2017
Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic
J Núñez, MJ Avedillo, M Jiménez, JM Quintana, A Todri-Sanial, E Corti, ...
Frontiers in Neuroscience 15, 655823, 2021
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J Núñez, AJ Ginés, EJ Peralías, A Rueda
2015 Conference on Design of Circuits and Integrated Systems (DCIS), 1-4, 2015
Improving speed of tunnel FETs logic circuits
MJ Avedillo, J Núñez
Electronics Letters 51 (21), 1702-1704, 2015
RTD–CMOS pipelined networks for reduced power consumption
J Núñez, MJ Avedillo, JM Quintana
IEEE transactions on nanotechnology 10 (6), 1217-1220, 2011
Simplified single-phase clock scheme for MOBILE networks
J Núñez, MJ Avedillo, JM Quintana
Electronics letters 47 (11), 648-650, 2011
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications
J Núñez, MJ Avedillo
IEEE Journal of the Electron Devices Society 5 (6), 530-534, 2017
Correct DC operation in RTD-based ternary inverters
J Nuniez, JM Quintana, MJ Avedillo
2007 2nd IEEE International Conference on Nano/Micro Engineered and …, 2007
Phase transition FETs for improved dynamic logic gates
MJ Avedillo, M Jiménez, J Núñez
IEEE Electron Device Letters 39 (11), 1776-1779, 2018
Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P Saraza-Canflanca, D Malagon, F Passos, A Toro, J Núñez, ...
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
Domino inspired MOBILE networks
J Núñez, MJ Avedillo, JM Quintana
Electronics letters 48 (5), 292-293, 2012
Power and speed evaluation of hyper-FET circuits
J Núñez, MJ Avedillo
IEEE Access 7, 6724-6732, 2018
Fast and area efficient multi-input Muller C-element based on MOS-NDR
J Núñez, JM Quintana, MJ Avedillo
2009 IEEE International Symposium on Circuits and Systems (ISCAS), 1811-1814, 2009
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