Juan Núñez-Martínez
Juan Núñez-Martínez
Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / Universidad de Sevilla)
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Cited by
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Year
Efficient realisation of MOS-NDR threshold logic gates
J Nunez, MJ Avedillo, JM Quintana
Electronics letters 45 (23), 1158-1160, 2009
222009
Comparison of TFETs and CMOS using optimal design points for power–speed tradeoffs
J Núñez, MJ Avedillo
IEEE Transactions on Nanotechnology 16 (1), 83-89, 2016
162016
Operation limits for RTD-based MOBILE circuits
JM Quintana, MJ Avedillo, J Nunez, HP Roldán
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (2), 350-363, 2008
142008
Comparative analysis of projected tunnel and CMOS transistors for different logic application areas
J Núñez, MJ Avedillo
IEEE Transactions on Electron Devices 63 (12), 5012-5020, 2016
132016
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J Núñez, MJ Avedillo, JM Quintana
112012
Improving speed of tunnel FETs logic circuits
MJ Avedillo, J Núñez
Electronics Letters 51 (21), 1702-1704, 2015
92015
RTD–CMOS pipelined networks for reduced power consumption
J Núñez, MJ Avedillo, JM Quintana
IEEE transactions on nanotechnology 10 (6), 1217-1220, 2011
92011
Simplified single-phase clock scheme for MOBILE networks
J Núñez, MJ Avedillo, JM Quintana
Electronics letters 47 (11), 648-650, 2011
82011
Insights into the operation of hyper-FET-based circuits
MJ Avedillo, J Núñez
IEEE Transactions on Electron Devices 64 (9), 3912-3918, 2017
72017
Correct DC operation in RTD-based ternary inverters
J Nuniez, JM Quintana, MJ Avedillo
2007 2nd IEEE International Conference on Nano/Micro Engineered and …, 2007
72007
Domino inspired MOBILE networks
J Núñez, MJ Avedillo, JM Quintana
Electronics letters 48 (5), 292-293, 2012
62012
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J Núñez, AJ Ginés, EJ Peralías, A Rueda
2015 Conference on Design of Circuits and Integrated Systems (DCIS), 1-4, 2015
52015
Novel dynamic gate topology for superpipelines in DSM technologies
J Núñez, MJ Avedillo, JM Quintana
2013 Euromicro Conference on Digital System Design, 280-283, 2013
52013
Limits to a correct evaluation in rtd-based ternary inverters
J Nunez, JM Quintana, MJ Avedillo
2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006
52006
Phase transition FETs for improved dynamic logic gates
MJ Avedillo, M Jiménez, J Núñez
IEEE Electron Device Letters 39 (11), 1776-1779, 2018
42018
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications
J Núñez, MJ Avedillo
IEEE Journal of the Electron Devices Society 5 (6), 530-534, 2017
42017
Assessing application areas for tunnel transistor technologies
MJ Avedillo, J Núñez
2015 Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2015
42015
Improving robustness of dynamic logic based pipelines
HJ Quintero, MJ Avedillo, J Núñez
2015 Conference on Design of Circuits and Integrated Systems (DCIS), 1-4, 2015
42015
Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements
J Núñez, MJ Avedillo, JM Quintana
IEEE Transactions on very large scale Integration (VLSI) Systems 22 (10 …, 2014
42014
Fast and area efficient multi-input Muller C-element based on MOS-NDR
J Núñez, JM Quintana, MJ Avedillo
2009 IEEE International Symposium on Circuits and Systems, 1811-1814, 2009
42009
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