Francesco Conti
Francesco Conti
Assistant Professor, University of Bologna
Verified email at - Homepage
Cited by
Cited by
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters
F Conti, L Benini
DATE 2015, 2015
PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision
F Conti, D Rossi, A Pullini, I Loi, L Benini
Journal of Signal Processing Systems 84 (3), 339-354, 2016
PULP: A parallel ultra low power platform for next generation IoT applications
D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015
A 64-mW DNN-based visual navigation engine for autonomous nano-drones
D Palossi, A Loquercio, F Conti, E Flamand, D Scaramuzza, L Benini
IEEE Internet of Things Journal 6 (5), 8357-8371, 2019
GAP-8: A RISC-V SoC for AI at the Edge of the IoT
E Flamand, D Rossi, F Conti, I Loi, A Pullini, F Rotenberg, L Benini
2018 IEEE 29th International Conference on Application-specific Systems …, 2018
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ...
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
XNOR neural engine: A hardware accelerator IP for 21.6-fJ/op binary neural network inference
F Conti, PD Schiavone, L Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
NEURAghe Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs
P Meloni, A Capotondi, G Deriu, M Brian, F Conti, D Rossi, L Raffo, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-24, 2018
Accelerated visual context classification on a low-power smartwatch
F Conti, D Palossi, R Andri, M Magno, L Benini
IEEE Transactions on Human-Machine Systems 47 (1), 19-30, 2016
Energy-Efficient Vision on the PULP Platform for Ultra-Low Power Parallel Computing
F Conti, D Rossi, A Pullini, I Loi, L Benini
Proceedings of 2014 IEEE International Workshop on Signal Processing Systems, 2014
PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors
A Garofalo, M Rusci, F Conti, D Rossi, L Benini
Philosophical Transactions of the Royal Society A 378 (2164), 20190155, 2020
Brain-inspired classroom occupancy monitoring on a low-power mobile platform
F Conti, A Pullini, L Benini
Proceedings of the IEEE Conference on Computer Vision and Pattern …, 2014
He-P2012: Architectural Heterogeneity Exploration on a Scalable Many-Core Platform
F Conti, C Pilkington, A Marongiu, L Benini
2014 IEEE 25th International Conference on Application-specific Systems …, 2014
Ultra low power deep-learning-powered autonomous nano drones
D Palossi, A Loquercio, F Conti, E Flamand, D Scaramuzza, L Benini
IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS 2018), 2018
Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference
F Conti, L Cavigelli, G Paulin, I Susmelj, L Benini
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018
A heterogeneous multicore system on chip for energy efficient brain inspired computing
A Pullini, F Conti, D Rossi, I Loi, M Gautschi, L Benini
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (8), 1094-1098, 2017
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA
P Meloni, G Deriu, F Conti, I Loi, L Raffo, L Benini
Proceedings of the ACM International Conference on Computing Frontiers, 376-383, 2016
Energy efficient parallel computing on the PULP platform with support for OpenMP
D Rossi, I Loi, F Conti, G Tagliavini, A Pullini, A Marongiu
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
A self-aware architecture for PVT compensation and power nap in near threshold processors
D Rossi, I Loi, A Pullini, C Müller, A Burg, F Conti, L Benini, P Flatresse
IEEE Design & Test 34 (6), 46-53, 2017
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