A real-time closed-loop setup for hybrid neural networks G Bontorin, S Renaud, A Garenne, L Alvado, G Le Masson, J Tomas 2007 29th Annual International Conference of the IEEE Engineering in …, 2007 | 41 | 2007 |
DHyANA: A NoC-based neural network hardware architecture PC Holanda, CRW Reinbrecht, G Bontorin, VV Bandeira, RAL Reis 2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016 | 16 | 2016 |
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC V Kerzérho, S Bernard, F Azaïs, M Comte, O Potin, C Shan, G Bontorin, ... Microelectronics Journal 44 (9), 840-843, 2013 | 14 | 2013 |
Bioelectronic sensing of insulin demand M Raoux, G Bontorin, Y Bornat, J Lang, S Renaud Biohybrid systems: nerves, interfaces, and machines, 191-202, 2011 | 11 | 2011 |
Low noise and low cost neural amplifiers G Bontorin, J Tomas, S Renaud 2007 14th IEEE International Conference on Electronics, Circuits and Systems …, 2007 | 10 | 2007 |
Low latency fpga implementation of izhikevich-neuron model V Bandeira, VL Costa, G Bontorin, RAL Reis System Level Design from HW/SW to Memory for Embedded Systems: 5th IFIP TC …, 2017 | 9 | 2017 |
A real-time setup for multisite signal recording and processing in living neural networks G Bontorin, C Lopez, Y Bornat, N Lewis, S Renaud, A Garenne, ... 2008 IEEE International Symposium on Circuits and Systems, 2953-2956, 2008 | 8 | 2008 |
Bioelectronics closed-loop for hybrid neural networks: towards a fully integrated approach G Bontorin Master thesis, University Bordeaux 1, 2006 | 6 | 2006 |
Global strategy to guaranty dependability of electrical medical implanted devices F Le Floch, S Bernard, G Bontorin, F Soulier, G Cathébras 2011 5th International IEEE/EMBS Conference on Neural Engineering, 515-518, 2011 | 5 | 2011 |
A real-time closed-loop setup allowing sensory feedback driven learning strategies A Garenne, A Maillard, L Alvado, J Tomas, G Bontorin, F Nagy, S Renaud, ... submitted to J. Neuroscience Methods, 2007 | 5 | 2007 |
Exploring more efficient architectures for multiple dynamic supply voltage designs M Terres, C Meinhardt, G Bontorin, R Reis 2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014 | 4 | 2014 |
A real-time system for multisite stimulation on living neural networks G Bontorin, A Garenne, J Tomas, C Lopez, FO Morin, S Renaud 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA …, 2009 | 4 | 2009 |
A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage M Terres, C Meinhardt, G Bontorin, R Reis 2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013 | 3 | 2013 |
Design of a bioelectronics hybrid system in real time and in closed loop G Bontorin, A Garenne, C Lopez, G Le Masson, S Renaud Electronics 16 (2), 136-144, 2012 | 3 | 2012 |
A new nonlinear global placement for FPGAs: The chaotic place E de Almeida Ramos, G Bontorin, R Reis IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2165-2174, 2019 | 2 | 2019 |
Chaotic synchronization of neural networks in FPGA E de Almeida Ramos, V Bandeira, R Reis, G Bontorin Computational Neuroscience: First Latin American Workshop, LAWCN 2017, Porto …, 2017 | 2 | 2017 |
Energy-efficient Level Shifter topology R Llanos, D Sousa, M Terres, G Bontorin, R Reis, M Johann 2015 25th International Workshop on Power and Timing Modeling, Optimization …, 2015 | 2 | 2015 |
Intelligent multielectrode arrays: improving spatiotemporal performances in hybrid (living-artificial), real-time, closed-loop systems G Bontorin Université Sciences et Technologies-Bordeaux I, 2010 | 2 | 2010 |
A nonlinear placement for FPGAs: The chaotic place E de Almeida Ramos, G Bontorin, R Reis 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 1 | 2018 |
Reducing the amount of transistors by gate merging LM da Silva, G Bontorin, R Reis 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 1 | 2018 |