Kourosh Gharachorloo
Kourosh Gharachorloo
Verified email at google.com
TitleCited byYear
Memory consistency and event ordering in scalable shared-memory multiprocessors
K Gharachorloo, D Lenoski, J Laudon, P Gibbons, A Gupta, J Hennessy
ACM SIGARCH Computer Architecture News 18 (2SI), 15-26, 1990
16431990
Shared memory consistency models: A tutorial
SV Adve, K Gharachorloo
computer 29 (12), 66-76, 1996
14161996
The stanford dash multiprocessor
D Lenoski, J Laudon, K Gharachorloo, WD Weber, A Gupta, J Hennessy, ...
Computer 25 (3), 63-79, 1992
13411992
The stanford flash multiprocessor
J Kuskin, D Ofelt, M Heinrich, J Heinlein, R Simoni, K Gharachorloo, ...
ACM SIGARCH Computer Architecture News 22 (2), 302-313, 1994
9821994
The directory-based cache coherence protocol for the DASH multiprocessor
D Lenoski, J Laudon, K Gharachorloo, A Gupta, J Hennessy
ACM SIGARCH Computer Architecture News 18 (2SI), 148-159, 1990
9081990
Piranha: a scalable architecture based on single-chip multiprocessing
LA Barroso, K Gharachorloo, R McNamara, A Nowatzyk, S Qadeer, ...
ACM SIGARCH Computer Architecture News 28 (2), 282-293, 2000
7182000
Memory system characterization of commercial workloads
LA Barroso, K Gharachorloo, E Bugnion
ACM SIGARCH Computer Architecture News 26 (3), 3-14, 1998
5041998
Shasta: A low overhead, software-only approach for supporting fine-grain shared memory
DJ Scales, K Gharachorloo, CA Thekkath
ACM SIGOPS Operating Systems Review 30 (5), 174-185, 1996
4331996
Performance evaluation of memory consistency models for shared-memory multiprocessors
K Gharachorloo, A Gupta, J Hennessy
ACM SIGARCH Computer Architecture News 19 (2), 245-257, 1991
3081991
Two techniques to enhance the performance of memory consistency models
K Gharachorloo, A Gupta, JL Hennessy
Computer Systems Laboratory, Stanford University, 1991
3041991
An analysis of database workload performance on simultaneous multithreaded processors
JL Lo, LA Barroso, SJ Eggers, K Gharachorloo, HM Levy, SS Parekh
ACM SIGARCH Computer Architecture News 26 (3), 39-50, 1998
2901998
Comparative evaluation of latency reducing and tolerating techniques
A Gupta, J Hennessy, K Gharachorloo, T Mowry, WD Weber
ACM SIGARCH Computer Architecture News 19 (3), 254-263, 1991
2631991
Scalable architecture based on single-chip multiprocessing
LA Barroso, K Gharachorloo, A Nowatzyk
US Patent 6,668,308, 2003
2502003
Performance of database workloads on shared-memory systems with out-of-order processors
P Ranganathan, K Gharachorloo, SV Adve, LA Barroso
ACM SIGPLAN Notices 33 (11), 307-318, 1998
2051998
Memory consistency models for shared-memory multiprocessors
K Gharachorloo
Stanford University, 1996
1841996
Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures
DJ Scales, K Gharachorloo
US Patent 5,933,598, 1999
182*1999
The performance impact of flexibility in the Stanford FLASH multiprocessor
M Heinrich, J Kuskin, D Ofelt, J Heinlein, J Baxter, JP Singh, R Simoni, ...
ACM SIGPLAN Notices 29 (11), 274-285, 1994
1821994
Architecture and design of AlphaServer GS320
K Gharachorloo, M Sharma, S Steely, S Van Doren
ACM Sigplan Notices 35 (11), 13-24, 2000
1712000
Integration of message passing and shared memory in the Stanford FLASH multiprocessor
J Heinlein, K Gharachorloo, S Dresser, A Gupta
ACM SIGPLAN Notices 29 (11), 38-50, 1994
1501994
Method and system for exclusive two-level caching in a chip-multiprocessor
LA Barroso, K Gharachorloo, A Nowatzyk
US Patent 6,725,334, 2004
1482004
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