Antonio Jose Acosta-Jimenez
Antonio Jose Acosta-Jimenez
Instituto de Microelectrónica de Sevilla (Universidad de Sevilla - CSIC)
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CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory–processing–learning–actuating system for high-speed visual object recognition and tracking
R Serrano-Gotarredona, M Oster, P Lichtsteiner, A Linares-Barranco, ...
IEEE transactions on neural networks 20 (9), 1417-1438, 2009
3322009
A neuromorphic cortical-layer microchip for spike-based event processing vision systems
R Serrano-Gotarredona, T Serrano-Gotarredona, A Acosta-Jimenez, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (12), 2548-2566, 2006
1192006
AER building blocks for multi-layer multi-chip neuromorphic vision systems
R Serrano-Gotarredona, M Oster, P Lichtsteiner, A Linares-Barranco, ...
Advances in neural information processing systems, 1217-1224, 2006
1092006
An event-driven multi-kernel convolution processor module for event-driven vision sensors
L Camunas-Mesa, C Zamarreno-Ramos, A Linares-Barranco, ...
IEEE Journal of Solid-State Circuits 47 (2), 504-517, 2011
942011
On real-time AER 2-D convolutions hardware for neuromorphic spike-based cortical processing
R Serrano-Gotarredona, T Serrano-Gotarredona, A Acosta-Jiménez, ...
IEEE Transactions on Neural Networks 19 (7), 1196-1219, 2008
822008
Logical modelling of delay degradation effect in static CMOS gates
MJ Bellido-Diaz, J Juan-Chico, AJ Acosta, M Valencia, JL Huertas
IEE Proceedings-Circuits, Devices and Systems 147 (2), 107-117, 2000
722000
A 3232 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
L Camunas-Mesa, A Acosta-Jimenez, C Zamarreno-Ramos, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (4), 777-790, 2010
582010
Simple binary random number generator
MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas
Electronics Letters 28 (7), 617-618, 1992
351992
A methodology for optimized design of secure differential logic gates for DPA resistant circuits
E Tena-Sánchez, J Castro, AJ Acosta
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (2 …, 2014
312014
SODS: A new CMOS differential-type structure
AJ Acosta, M Valencia, A Barriga, MJ Bellido, JL Huertas
IEEE journal of solid-state circuits 30 (7), 835-838, 1995
271995
Optimization of clock-gating structures for low-leakage high-performance applications
J Castro, P Parra, AJ Acosta
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
242010
A mixed-signal integrated circuit for FM-DCSK modulation
M Delgado-Restituto, AJ Acosta, A Rodríguez-Vázquez
IEEE Journal of solid-state circuits 40 (7), 1460-1471, 2005
232005
Degradation delay model extension to CMOS gates
J Juan-Chico, MJ Bellido, P Ruiz-de-Clavijo, AJ Acosta, M Valencia
International Workshop on Power and Timing Modeling, Optimization and …, 2000
222000
Inertial and degradation delay model for CMOS logic gates
J Juan-Chico, PR de Clavijo, MJ Bellido, AJ Acosta, M Valenia
2000 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 459-462, 2000
222000
A VHDL-based Methodology for the Design and Verification of Pipeline A/D Converters
E Peralías, AJ Acosta, A Rueda, JL Huertas
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000
222000
A simple binary random number generator: new approaches for cmos vlsi
MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems …, 1992
201992
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
AJ Acosta, T Addabbo, E Tena‐Sánchez
International Journal of Circuit Theory and Applications 45 (2), 145-169, 2017
182017
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
PR de Clavijo Vazquez, J Juan-Chico, MJ Bellido, A Acosta, M Valencia
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
182001
Analysis of high-performance flip-flops for submicron mixed-signal applications
R Jiménez, P Parra, P Sanmartín, AJ Acosta
Analog Integrated Circuits and Signal Processing 33 (2), 145-156, 2002
162002
Analog/mixed-signal IP modeling for design reuse
NM Madrid, E Peralías, A Acosta, A Rueda
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
162001
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