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Tejasvi Anand
Tejasvi Anand
Assistant Professor, Oregon State University
Verified email at eecs.oregonstate.edu - Homepage
Title
Cited by
Cited by
Year
A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC
A Elkholy, T Anand, WS Choi, A Elshazly, PK Hanumolu
IEEE Journal of Solid-State Circuits 50 (4), 867-881, 2015
1152015
A VCO Based Highly Digital Temperature Sensor With 0.034° C/mV Supply Sensitivity
T Anand, KAA Makinwa, PK Hanumolu
IEEE Journal of Solid-State Circuits 51 (11), 2651-2663, 2016
782016
A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition
G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ...
IEEE Journal of Solid-State Circuits 51 (2), 428-439, 2015
582015
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
A Elkholy, M Talegaonkar, T Anand, PK Hanumolu
IEEE Journal of Solid-State Circuits 50 (12), 3160-3174, 2015
582015
A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method
RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ...
IEEE Journal of Solid-State Circuits 50 (4), 882-895, 2015
552015
A 75dB DR 50MHz BW 3rdorder CT-ΔΣ modulator using VCO-based integrators
B Young, K Reddy, S Rao, A Elshazly, T Anand, PK Hanumolu
2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014
422014
8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS
G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
412014
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrmsintegrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in …
A Elkholy, M Talegaonkar, T Anand, PK Hanumolu
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
352015
A self-referenced VCO-based temperature sensor with 0.034° C/mV supply sensitivity in 65nm CMOS
T Anand, KAA Makinwa, PK Hanumolu
2015 Symposium on VLSI Circuits (VLSI Circuits), C200-C201, 2015
332015
Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator
S Bose, T Anand, ML Johnston
IEEE Journal of Solid-State Circuits 54 (10), 2867-2878, 2019
312019
An 8-to-1 bit 1-MS/s SAR ADC with VGA and integrated data compression for neural recording
V Chaturvedi, T Anand, B Amrutur
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (11 …, 2013
262013
A burst-mode digital receiver with programmable input jitter filtering for energy proportional links
WS Choi, T Anand, G Shu, A Elshazly, PK Hanumolu
IEEE Journal of Solid-State Circuits 50 (3), 737-748, 2015
252015
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links
T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu
IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, 2015
242015
A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver
S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ...
IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2017
172017
A 0.5-to-0.9 V, 3-to-16Gb/s, 1.6-to-3.1 pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in …
A Ramachandran, T Anand
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 268-270, 2018
162018
A 3.5 mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting
S Bose, T Anand, ML Johnston
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
152019
Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump
S Bose, T Anand, ML Johnston
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018
152018
29.4 A 16Gb/s 3.6 pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS
A Ramachandran, A Natarajan, T Anand
2017 IEEE International Solid-State Circuits Conference (ISSCC), 488-489, 2017
142017
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time
T Anand, M Talegaonkar, A Elshazly, B Young, PK Hanumolu
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
142013
A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS
S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353, 2015
132015
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