Andre Reis
Andre Reis
Institute of Informatics - UFRGS
Verified email at inf.ufrgs.br - Homepage
TitleCited byYear
Open Cell Library in 15nm FreePDK Technology
M Martins, JM Matos, RP Ribas, A Reis, G Schlinker, L Rech, J Michelsen
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
992015
Boolean factoring with multi-objective goals
MGA Martins, L Rosa Jr, AB Rasmussen, RP Ribas, A Reis
Computer Design (ICCD), 2010 IEEE International Conference on, 229-234, 2010
542010
Classifying n-input Boolean functions
VP Correia, AI Reis
VII Workshop Iberchip, 58, 2001
392001
DAG based library-free technology mapping
FS Marques, LS Rosa Jr, RP Ribas, SS Sapatnekar, AI Reis
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 293-298, 2007
382007
KL-cuts: a new approach for logic synthesis targeting multiple output blocks
O Martinello, FS Marques, RP Ribas, AI Reis
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 …, 2010
342010
BTI, HCI and TDDB aging impact in flip–flops
C Nunes, PF Butzen, AI Reis, RP Ribas
Microelectronics Reliability 53 (9-11), 1355-1359, 2013
322013
Associating CMOS transistors with BDD arcs for technology mapping
A Reis, M Robert, D Auvergne, R Reis
Electronics Letters 31 (14), 1118-1120, 1995
321995
Exact lower bound for the number of switches in series to implement a combinational logic cell
FR Schneider, RP Ribas, SS Sapatnekar, AI Reis
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005
312005
Advanced technology mapping for standard-cell generators
V Correia, A Reis
Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems …, 2004
302004
Library free technology mapping
AI Reis, R Reis, D Auvergne, M Robert
VLSI: Integrated Systems on Silicon, 303-314, 1997
301997
Graph-based transistor network generation method for supergate design
VN Possani, V Callegaro, AI Reis, RP Ribas, F de Souza Marques, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 692-705, 2015
252015
Switch level optimization of digital CMOS gate networks
LS da Rosa, FR Schneider, RP Ribas, AI Reis
2009 10th International Symposium on Quality Electronic Design, 324-329, 2009
252009
Unified theory to build cell-level transistor networks from BDDs [logic synthesis]
REB Poli, FR Schneider, RP Ribas, AI Reis
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
252003
Covering strategies for library free technology mapping
AI Reis
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat …, 1999
241999
Power consumption analysis in static cmos gates
A Wiltgen, KA Escobar, AI Reis, RP Ribas
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
222013
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
M Moreira, N Calazans, A Silva, M Martins, A Reis, R Ribas
International Symposium on Asynchronous Circuits and Systems (ASYNC), Potsdam, 2014
212014
Functional composition: A new paradigm for performing logic synthesis
MGA Martins, RP Ribas, AI Reis
Quality Electronic Design (ISQED), 2012 13th International Symposium on, 236-242, 2012
202012
A comparative study of CMOS gates with minimum transistor stacks
LS da Rosa Junior, AI Reis, RP Ribas, FS Marques, FR Schneider
Proceedings of the 20th annual conference on Integrated circuits and systems …, 2007
202007
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
PF Butzen, LS da Rosa Jr, EJD Chiappetta Filho, AI Reis, RP Ribas
Microelectronics Journal 41 (4), 247-255, 2010
192010
Scheduling policy costs on a JAVA microcontroller
L Rosa, F Wagner, L Carro, A Carissimi, A Reis
On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 520-533, 2003
192003
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Articles 1–20