| TCP onloading for data center servers G Regnier, S Makineni, I Illikkal, R Iyer, D Minturn, R Huggahalli, D Newell, ... Computer 37 (11), 48-58, 2004 | 301 | 2004 |
| CHOP: Adaptive filter-based dram caching for CMP server platforms X Jiang, N Madan, L Zhao, M Upton, R Iyer, S Makineni, D Newell, ... High Performance Computer Architecture (HPCA), 2010 IEEE 16th International …, 2010 | 198 | 2010 |
| Priority aware selective cache allocation R Iyer, R Milekal, D Newell, L Zhao US Patent 7,802,057, 2010 | 142 | 2010 |
| CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs B Li, L Zhao, R Iyer, LS Peh, M Leddige, M Espig, SE Lee, D Newell Journal of Parallel and Distributed Computing 71 (5), 700-713, 2011 | 139 | 2011 |
| Exploring DRAM cache architectures for CMP server platforms L Zhao, R Iyer, R Illikkal, D Newell 2007 25th International Conference on Computer Design, 55-62, 2007 | 129 | 2007 |
| RTP payload format for the 1998 version of ITU-T Rec. H. 263 video (H. 263+) C Bormann, L Cline, G Deisher, T Gardos, C Maciocco, D Newell, J Ott, ... | 121* | 1998 |
| Hardware management systems for disaggregated rack architectures in virtual server rack deployments R Kulkarni, VM Sekhar, M Gunti, R Yavatkar, D Newell, T Sridhar US Patent 10,348,574, 2019 | 103 | 2019 |
| An in-depth analysis of the impact of processor affinity on network performance A Foong, J Fung, D Newell Proceedings. 2004 12th IEEE International Conference on Networks (ICON 2004 …, 2004 | 101 | 2004 |
| Packet coalescing S Makineni, R Iyer, D Minturn, S Sen, D Newell, L Zhao US Patent 7,620,071, 2009 | 97 | 2009 |
| Packet coalescing S Makineni, R Iyer, D Minturn, S Sen, D Newell, L Zhao US Patent 7,620,071, 2009 | 97 | 2009 |
| Packet coalescing S Makineni, R Iyer, D Minturn, S Sen, D Newell, L Zhao EP Patent 1,813,084, 2008 | 97 | 2008 |
| Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy N Madan, L Zhao, N Muralimanohar, A Udipi, R Balasubramonian, R Iyer, ... 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 93 | 2009 |
| Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions K Varadarajan, SK Nandy, V Sharda, A Bharadwaj, R Iyer, S Makineni, ... 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 91 | 2006 |
| Exploring the cache design space for large scale CMPs L Hsu, R Iyer, S Makineni, S Reinhardt, D Newell ACM SIGARCH Computer Architecture News 33 (4), 24-33, 2005 | 89 | 2005 |
| Dynamic quality of service (QoS) for a shared cache WC Hasenplaugh, L Zhao, R Iyer, R Illikkal, S Makineni, D Newell, ... US Patent 7,725,657, 2010 | 74 | 2010 |
| Performance, area and bandwidth implications on large-scale CMP cache design L Zhao, R Iyer, S Makineni, J Moses, R Illikkal, D Newell Proceedings of the Work. on Chip Multiprocessor Memory Systems and Interconnects, 2007 | 59 | 2007 |
| Providing quality of service (QoS) for cache architectures using priority information L Zhao, R Iyer, R Illikkal, S Makineni, D Newell US Patent 7,899,994, 2011 | 57 | 2011 |
| Architectural characterization of processor affinity in network processing A Foong, J Fung, D Newell, S Abraham, P Irelan, A Lopez-Estrada IEEE International Symposium on Performance Analysis of Systems and Software …, 2005 | 54 | 2005 |
| Providing application-level information for use in cache management R Illikkal, R Iyer, L Zhao, D Newell, C Lebsack, QA Jacobson, S Srinivas, ... US Patent 7,991,956, 2011 | 52 | 2011 |
| Accelerating mobile augmented reality on a handheld platform SE Lee, Y Zhang, Z Fang, S Srinivasan, R Iyer, D Newell 2009 IEEE International Conference on Computer Design, 419-426, 2009 | 50 | 2009 |
