| DRAM refresh mechanisms, penalties, and trade-offs I Bhati, MT Chang, Z Chishti, SL Lu, B Jacob IEEE Transactions on Computers 65 (1), 108-121, 2015 | 159 | 2015 |
| Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions I Bhati, Z Chishti, SL Lu, B Jacob Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 125 | 2015 |
| Techniques to reduce memory cell refreshes for a memory device ZA Chishti, IS Bhati, SLL Lu US Patent 9,418,723, 2016 | 92 | 2016 |
| Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 67 | 2018 |
| Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling I Bhati, Z Chishti, B Jacob International Symposium on Low Power Electronics and Design (ISLPED), 205-210, 2013 | 32 | 2013 |
| Coordinating power mode switching and refresh operations in a memory device ZA Chishti, I Bhati US Patent 9,001,608, 2015 | 30 | 2015 |
| An integrated simulation infrastructure for the entire memory hierarchy: Cache, dram, nonvolatile memory, and disk J Stevens, P Tschirhart, MT Chang, I Bhati, P Enns, J Greensky, Z Chisti, ... Intel Technology Journal 17 (1), 184-200, 2013 | 28 | 2013 |
| Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein … IS Bhati, H Liu, J Gaur, K Korgaonkar, S Manipatruni, S Subramoney, ... US Patent 10,331,582, 2019 | 12 | 2019 |
| Overcoming interconnect scaling challenges using novel process and design solutions to improve both high-speed and low-power computing modes K Vaidyanathan, DH Morris, UE Avci, IS Bhati, L Subramanian, J Gaur, ... 2017 IEEE International Electron Devices Meeting (IEDM), 20.1. 1-20.1. 4, 2017 | 9 | 2017 |
| Scalable and energy efficient DRAM refresh techniques IS Bhati University of Maryland, College Park, 2014 | 8 | 2014 |
| Similarity search in the blink of an eye with compressed indices C Aguerrebere, I Bhati, M Hildebrand, M Tepper, T Willke arXiv preprint arXiv:2304.04759, 2023 | 6 | 2023 |
| Memory aware reordered source IS Bhati, U Dhawan, J Gaur, S Subramoney US Patent 10,866,902, 2020 | 5 | 2020 |
| Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ... IEEE, 315ś327, 2018 | 5 | 2018 |
| Method and apparatus for reducing write congestion in non-volatile memory based last level caches KK Korgaonkar, IS Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ... US Patent App. 15/475,197, 2018 | 4 | 2018 |
| A journaled, NAND-flash main-memory system B Jacob, I Bhati, MT Chang, P Rosenfeld, J Stevens, P Tschirhart, ... Electrical and Computer Engineering Dept., Systems and Computer Architecture …, 2010 | 4 | 2010 |
| Instructions and logic for vector multiply add with zero skipping S Pal, S Avancha, I Bhati, WY Chen, D Das, A Garg, CS Gurram, J Gu, ... US Patent 11,314,515, 2022 | 3 | 2022 |
| Locally-adaptive quantization for streaming vector search C Aguerrebere, M Hildebrand, IS Bhati, T Willke, M Tepper arXiv preprint arXiv:2402.02044, 2024 | 1 | 2024 |
| LeanVec: Search your vectors faster by making them fit M Tepper, IS Bhati, C Aguerrebere, M Hildebrand, T Willke arXiv preprint arXiv:2312.16335, 2023 | 1 | 2023 |
| To cache or to bypass? A fine balance in the emerging memory technology era K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ... NVM, 2019 | 1 | 2019 |
| Locally-adaptive vector quantization for similarity search MCA Otegui, I Bhati, M Hildebrand, M Tepper, T Willke US Patent App. 18/364,664, 2024 | | 2024 |
Zeshan ChishtiStaff Research Scientist, Intel CorporationVerified email at intel.com
