Moinuddin Qureshi
TitleCited byYear
Scalable high performance main memory system using phase-change memory technology
MK Qureshi, V Srinivasan, JA Rivers
ACM SIGARCH Computer Architecture News 37 (3), 24-33, 2009
13722009
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
MK Qureshi, YN Patt
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
11642006
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
Proceedings of the 42nd annual IEEE/ACM international symposium on …, 2009
7052009
Adaptive insertion policies for high performance caching
MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer
ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007
7022007
Adaptive insertion policies for managing shared caches
A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer
Proceedings of the 17th international conference on Parallel architectures …, 2008
3542008
Accelerating critical section execution with asymmetric multi-core architectures
MA Suleman, O Mutlu, MK Qureshi, YN Patt
ACM SIGARCH Computer Architecture News 37 (1), 253-264, 2009
3372009
A case for MLP-aware cache replacement
MK Qureshi, DN Lynch, O Mutlu, YN Patt
33rd International Symposium on Computer Architecture (ISCA'06), 167-178, 2006
3322006
Improving read performance of phase change memories via write cancellation and write pausing
MK Qureshi, MM Franceschini, LA Lastras-Montano
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
3022010
The V-Way cache: demand-based associativity via global replacement
MK Qureshi, D Thompson, YN Patt
32nd International Symposium on Computer Architecture (ISCA'05), 544-555, 2005
2612005
Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design
MK Qureshi, GH Loh
Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on …, 2012
2312012
Morphable memory system: A robust architecture for exploiting multi-level phase change memories
MK Qureshi, MM Franceschini, LA Lastras-Montaño, JP Karidis
ACM SIGARCH Computer Architecture News 38 (3), 153-162, 2010
2032010
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
MA Suleman, MK Qureshi, YN Patt
ACM Sigplan Notices 43 (3), 277-286, 2008
2002008
A tagless coherence directory
J Zebchuk, V Srinivasan, MK Qureshi, A Moshovos
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
1612009
PreSET: improving performance of phase change memories by exploiting asymmetry in write times
MK Qureshi, MM Franceschini, A Jagmohan, LA Lastras
ACM SIGARCH Computer Architecture News 40 (3), 380-391, 2012
1512012
AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
MK Qureshi, DH Kim, S Khan, PJ Nair, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
1432015
ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
PJ Nair, DH Kim, MK Qureshi
ACM SIGARCH Computer Architecture News 41 (3), 72-83, 2013
1372013
Adaptive spill-receive for robust high-performance caching in CMPs
MK Qureshi
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
1312009
Pay-As-You-Go: low-overhead hard-error correction for phase change memories
MK Qureshi
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
1292011
NVRAM-aware logging in transaction systems
J Huang, K Schwan, MK Qureshi
Proceedings of the VLDB Endowment 8 (4), 389-400, 2014
1232014
Phase change memory: From devices to systems
MK Qureshi, S Gurumurthi, B Rajendran
Synthesis Lectures on Computer Architecture 6 (4), 1-134, 2011
1102011
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Articles 1–20