Peter Jamieson
Peter Jamieson
Associate Professor of Computer Engineering, Miami University
Verified email at miamioh.edu - Homepage
Title
Cited by
Cited by
Year
The VTR project: architecture and CAD for FPGAs from verilog to routing
J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
3212012
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
J Luu, I Kuon, P Jamieson, T Campbell, A Ye, WM Fang, K Kent, J Rose
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (4), 1-23, 2011
3172011
Odin ii-an open-source verilog hdl synthesis tool for cad research
P Jamieson, KB Kent, F Gharibian, L Shannon
2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010
1802010
Arduino for Teaching Embedded Systems. Are Computer Scientists and Engineering Educators Missing the Boat?
P Jamieson
1522011
More Missing the Boat - Arduino, Raspberry Pi, and Small Prototyping Boards and Engineering Education Needs Them
P Jamieson, J Herdtner
45th Frontiers in Education Conference, 2015
802015
An energy and power consumption analysis of FPGA routing architectures
P Jamieson, W Luk, SJE Wilton, GA Constantinides
2009 International Conference on Field-Programmable Technology, 324-327, 2009
752009
Enhancing the area efficiency of FPGAs with hard circuits using shadow clusters
PA Jamieson, J Rose
IEEE transactions on very large scale integration (VLSI) systems 18 (12 …, 2009
602009
Enhancing the area efficiency of FPGAs with hard circuits using shadow clusters
PA Jamieson, J Rose
IEEE transactions on very large scale integration (VLSI) systems 18 (12 …, 2009
602009
A verilog RTL synthesis tool for heterogeneous FPGAs
P Jamieson, J Rose
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
492005
Harnessing Human Computation Cycles for the FPGA Placement Problem.
L Terry, V Roitch, S Tufail, K Singh, O Taraq, W Luk, P Jamieson
ERSA 9, 188-194, 2009
272009
Using Modern Graph Analysis Techniques on Mind Maps to Help Quantify Learning
PA Jamieson
Frontiers in Education, 2012
222012
Revisiting Genetic Algorithms for the FPGA Placement Problem.
P Jamieson
GEM, 16-22, 2010
172010
Benchmarking reconfigurable architectures in the mobile domain
P Jamieson, T Becker, W Luk, PYK Cheung, T Rissa, T Pitkanen
2009 17th IEEE Symposium on Field Programmable Custom Computing Machines …, 2009
142009
Mapping multiplexers onto hard multipliers in FPGAs
P Jamieson, J Rose
The 3rd International IEEE-NEWCAS Conference, 2005., 323-326, 2005
132005
Architecting hard crossbars on FPGAs and increasing their area efficiency with shadow clusters
P Jamieson, J Rose
2007 International Conference on Field-Programmable Technology, 57-64, 2007
122007
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
P Jamieson, T Becker, PYK Cheung, W Luk, T Rissa, T Pitkänen
ACM Transactions on Design Automation of Electronic Systems (TODAES) 15 (2 …, 2010
112010
Cables: Thread control and memory management extensions for shared virtual memory clusters
P Jamieson, A Bilas
Proceedings Eighth International Symposium on High Performance Computer …, 2002
112002
Ready: A fine-grained multithreading overlay framework for modern cpu-fpga dataflow applications
LBD Silva, R Ferreira, M Canesche, MM Menezes, MD Vieira, J Penha, ...
ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-20, 2019
92019
Supergenes in a Genetic Algorithm for Heterogeneous FPGA Placement
P Jamieson, F Gharibian, L Shannon
IEEE Congress on Evolutionary Computation, 2013
92013
Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators
R Collier, C Fobel, R Pattison, G Grewal, S Areibi, P Jamieson
Evolutionary Intelligence 7 (4), 183-200, 2014
82014
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Articles 1–20