ALIGN: Open-source analog layout automation from the ground up K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 81 | 2019 |
A customized graph neural network model for guiding analog IC placement Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, SS Sapatnekar, R Harjani, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 71 | 2020 |
GANA: Graph convolutional network based automated netlist annotation for analog circuits K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2020 | 66 | 2020 |
ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 43 | 2020 |
Exploring a machine learning approach to performance driven analog IC placement Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, S Sapatnekar, R Harjani, ... 2020 IEEE computer society annual symposium on VLSI (ISVLSI), 24-29, 2020 | 26 | 2020 |
Common-centroid layouts for analog circuits: Advantages and limitations AK Sharma, M Madhusudan, SM Burns, P Mukherjee, S Yaldiz, R Harjani, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 24 | 2021 |
Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits A Sharma, N Alam, S Dasgupta, A Bulusu IEEE Transactions on Electron Devices 63 (6), 2517 - 2523, 2016 | 16 | 2016 |
Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-memory Computational Platform M Zabihi, AK Sharma, MG Mankalale, ZI Chowdhury, Z Zhao, S Resch, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2020 | 14 | 2020 |
A circuit attention network-based actor-critic learning approach to robust analog transistor sizing Y Li, Y Lin, M Madhusudan, A Sharma, S Sapatnekar, R Harjani, J Hu 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), 1-6, 2021 | 13 | 2021 |
Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design A Sharma, N Alam, A Bulusu IEEE Transactions on Electron Devices 9 (99), 1-9, 2017 | 13 | 2017 |
BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective N Chauhan, N Bagga, S Banchhor, C Garg, A Sharma, A Datta, ... Nanotechnology 33 (8), 085203, 2021 | 12 | 2021 |
From specification to silicon: Towards analog/mixed-signal design automation using surrogate NN models with transfer learning J Liu, S Su, M Madhusudan, M Hassanpourghadi, S Saunders, Q Zhang, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 12 | 2021 |
Investigation of trap-induced performance degradation and restriction on higher ferroelectric thickness in negative capacitance FDSOI FET C Garg, N Chauhan, A Sharma, S Banchhor, A Doneria, S Dasgupta, ... IEEE Transactions on Electron Devices 68 (10), 5298-5304, 2021 | 12 | 2021 |
Common-centroid layout for active and passive devices: A review and the road ahead N Karmokar, M Madhusudan, AK Sharma, R Harjani, MPH Lin, ... 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 114-121, 2022 | 9 | 2022 |
Constructive common-centroid placement and routing for binary-weighted capacitor arrays N Karmokar, AK Sharma, J Poojary, M Madhusudan, R Harjani, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 166-171, 2022 | 7 | 2022 |
Fast and efficient constraint evaluation of analog layout using machine learning models T Dhar, J Poojary, Y Li, K Kunal, M Madhusudan, AK Sharma, SD Manasi, ... Proceedings of the 26th Asia and South Pacific design automation conference …, 2021 | 7 | 2021 |
A Variation Aware Timing Model for a 2-Input NAND Gate and Its Use in Sub-65nm CMOS Standard Cell Characterization B Kaur, A Sharma, SK Alam, Naushad, Manhas, A Bulusu Microelectronics Journal 53 (7), 45-55, 2016 | 7 | 2016 |
Performance-aware common-centroid placement and routing of transistor arrays in analog circuits AK Sharma, M Madhusudan, SM Burns, S Yaldiz, P Mukherjee, R Harjani, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 6 | 2021 |
The ALIGN open-source analog layout generator: V1. 0 and beyond T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020 | 6 | 2020 |
Effective drive current for near-threshold CMOS circuits’ performance evaluation: Modeling to circuit design techniques A Sharma, N Alam, A Bulusu IEEE Transactions on Electron Devices 65 (6), 2413-2421, 2018 | 6 | 2018 |