SystemVerilog modeling of SFQ and AQFP circuits RN Tadros, A Fayyazi, M Pedram, PA Beerel
IEEE Transactions on Applied Superconductivity 30 (2), 1-13, 2019
21 2019 A robust and self-adaptive clocking technique for SFQ circuits RN Tadros, PA Beerel
IEEE Transactions on Applied Superconductivity 28 (7), 1-11, 2018
21 2018 A robust and tree-free hybrid clocking technique for RSFQ circuits-CSR application RN Tadros, PA Beerel
2017 16th International Superconductive Electronics Conference (ISEC), 1-4, 2017
19 2017 A fine-grained, uniform, energy-efficient delay element for FD-SOI technologies A Singhvi, MT Moreira, RN Tadros, NLV Calazans, PA Beerel
2015 IEEE Computer Society Annual Symposium on VLSI, 27-32, 2015
18 2015 Analysis and design of delay lines for dynamic voltage scaling applications RN Tadros, W Hua, M Gibiluka, MT Moreira, NLV Calazans, PA Beerel
2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems …, 2016
11 2016 Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks AH Elsayed, RN Tadros, M Ghoneima, Y Ismail
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2752-2755, 2014
11 2014 Low area, low power, robust, highly sensitive error detecting latch for resilient architectures W Hua, RN Tadros, PA Beerel
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
10 2016 A low-power low-area error-detecting latch for resilient architectures in 28-nm FDSOI RN Tadros, W Hua, MT Moreira, NLV Calazans, PA Beerel
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (9), 858-862, 2016
9 2016 A robust and self-adaptive clocking technique for RSFQ circuits—The architecture RN Tadros, PA Beerel
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
8 2018 Optimizing (HC) LC, A Robust Clock Distribution Network For SFQ Circuits RN Tadros, PA Beerel
IEEE Transactions on Applied Superconductivity 30 (1), 1-11, 2019
6 2019 A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks RN Tadros, AH Elsayed, M Ghoneima, Y Ismail
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1520-1523, 2014
6 2014 A fine-grain, uniform, energy-efficient delay element for 2-phase bundled-data circuits A Singhvi, MT Moreira, RN Tadros, NLV Calazans, PA Beerel
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (2), 1-23, 2016
5 2016 2 ps resolution, fine‐grained delay element in 28 nm FDSOI W Hua, RN Tadros, P Beerel
Electronics Letters 51 (23), 1848-1850, 2015
5 2015 A theoretical foundation for timing synchronous systems using asynchronous structures RN Tadros, PA Beerel
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (2 …, 2020
3 2020 A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme RN Tadros, AH Ahmed, M Ghoneima, Y Ismail
5th International Conference on Energy Aware Computing Systems …, 2015
3 2015 Clocking solutions for SFQ circuits RN Tadros
University of Southern California, 2019
2 2019 Ultra‐low power pass‐transistor‐logic‐based delay line design for sub‐threshold applications RN Tadros, N Dasari, PA Beerel
Electronics Letters 52 (23), 1910-1912, 2016
2 2016 Using asynchronous clock distribution networks for timing SFQ circuits RN Tadros, PA Beerel
Asynchronous Circuit Applications, 269, 2020
2020 A Clock Synthesis Algorithm for Hierarchical Chains of Homogeneous Clover-Leaves Clock Networks for Single Flux Quantum Logic Circuits SN Shahsavani, RN Tadros, PA Beerel, M Pedram
2019 IEEE International Superconductive Electronics Conference (ISEC), 1-3, 2019
2019 A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies PA Beerel, NLV Calazans, RN Tadros, MT Moreira, A Singhvi
Proceedings of the ISVLSI 2015, 2015, França., 2015
2015