| A study of an infrastructure for research and development of many-core processors K Uehara, S Sato, T Miyoshi, K Kise 2009 International Conference on Parallel and Distributed Computing …, 2009 | 29 | 2009 |
| An efficient and scalable implementation of sliding-window aggregate operator on fpga Y Oge, M Yoshimi, T Miyoshi, H Kawashima, H Irie, T Yoshinaga 2013 First International Symposium on Computing and Networking, 112-121, 2013 | 21 | 2013 |
| FLAT: A GPU programming framework to provide embedded MPI T Miyoshi, H Irie, K Shima, H Honda, M Kondo, T Yoshinaga Proceedings of the 5th Annual Workshop on General Purpose Processing with …, 2012 | 20 | 2012 |
| A coarse grain reconfigurable processor architecture for stream processing engine T Miyoshi, H Kawashima, Y Terada, T Yoshinaga 2011 21st International Conference on Field Programmable Logic and …, 2011 | 19 | 2011 |
| An implementation of handshake join on FPGA Y Oge, T Miyoshi, H Kawashima, T Yoshinaga 2011 Second International Conference on Networking and Computing, 95-104, 2011 | 15 | 2011 |
| An efficient path setup for a photonic network-on-chip CAD Adi, H Matsutani, M Koibuchi, H Irie, T Miyoshi, T Yoshinaga 2010 First International Conference on Networking and Computing, 156-161, 2010 | 15 | 2010 |
| A fast handshake join implementation on FPGA with adaptive merging network Y Oge, T Miyoshi, H Kawashima, T Yoshinaga Proceedings of the 25th International Conference on Scientific and …, 2013 | 14 | 2013 |
| SimMips: A MIPS system simulator N Fujieda, T Miyoshi, K Kise Proc. WCAE, 32-39, 2009 | 13 | 2009 |
| Multi-gpu acceleration of optical flow computation in visual functional simulation J Ohmura, A Egashira, S Satoh, T Miyoshi, H Irie, T Yoshinaga 2011 Second International Conference on Networking and Computing, 228-234, 2011 | 12 | 2011 |
| Design and implementation of a handshake join architecture on FPGA Y Oge, T Miyoshi, H Kawashima, T Yoshinaga IEICE TRANSACTIONS on Information and Systems 95 (12), 2919-2927, 2012 | 11 | 2012 |
| Parallel matrix-matrix multiplication based on hpl with a gpu-accelerated pc cluster Q Wang, J Ohmura, S Axida, T Miyoshi, H Irie, T Yoshinaga 2010 First International Conference on Networking and Computing, 243-248, 2010 | 9 | 2010 |
| Wire-speed implementation of sliding-window aggregate operator over out-of-order data streams Y Oge, M Yoshimi, T Miyoshi, H Kawashima, H Irie, T Yoshinaga 2013 IEEE 7th International Symposium on Embedded Multicore Socs, 55-60, 2013 | 8 | 2013 |
| A consideration of window join operator over data streams by using FPGA Y Terada, T Miyoshi, H Kawashima, T Yoshinaga IEICE Technical Report; IEICE Tech. Rep. 110 (362), 181-186, 2011 | 7 | 2011 |
| Hardware acceleration with multi-threading of java-based high level synthesis tool Y Ishikawa, K Yanai, K Koike, T Miyoshi, H Nakajo Proceedings of the 8th International Symposium on Highly Efficient …, 2017 | 6 | 2017 |
| Using Cacheline Reuse Characteristics for Prefetcher Throttling H Irie, T Miyoshi, G Honjo, K Hiraki, T Yoshinaga IEICE TRANSACTIONS on Information and Systems 95 (12), 2928-2938, 2012 | 5 | 2012 |
| Pattern-based systematic task mapping for many-core processors S Sano, M Sano, S Sato, T Miyoshi, K Kise 2010 First International Conference on Networking and Computing, 173-178, 2010 | 5 | 2010 |
| Codie: Continuation-based overlapping data-transfers with instruction execution T Miyoshi, K Kise, H Irie, T Yoshinaga 2010 First International Conference on Networking and Computing, 71-77, 2010 | 5 | 2010 |
| Design and evaluation of a configurable query processing hardware for data streams Y Oge, M Yoshimi, T Miyoshi, H Kawashima, H Irie, T Yoshinaga IEICE TRANSACTIONS on Information and Systems 98 (12), 2207-2217, 2015 | 4 | 2015 |
| FPGA-based implementation of sliding-window aggregates over disordered data streams Y Oge, M Yoshimi, T Miyoshi, H Kawashima, H Irie, T Yoshinaga IEICE Technical Report; IEICE Tech. Rep. 112 (376), 105-110, 2013 | 4 | 2013 |
| Design and implementation of a merging network architecture for handshake join operator on FPGA Y Oge, T Miyoshi, H Kawashima, T Yoshinaga 2012 IEEE 6th International Symposium on Embedded Multicore SoCs, 84-91, 2012 | 4 | 2012 |
