Mikel Fernandez
TitleCited byYear
Assessing the Suitability of the NGMP Multi-core Processor in the Space Domain
M Fernández, R Gioiosa, E Quiñones, L Fossati, M Zulianello, FJ Cazorla
EMSOFT 2012, 175, 2012
Speculative alias analysis for executable code
M Fernández, R Espasa
Proceedings. International Conference on Parallel Architectures and …, 2002
PROXIMA: Improving measurement-based timing analysis through randomisation and probabilistic analysis
FJ Cazorla, J Abella, J Andersson, T Vardanega, F Vatrinet, I Bate, ...
2016 Euromicro Conference on Digital System Design (DSD), 276-285, 2016
Bounding resource contention interference in the next-generation microprocessor (NGMP)
J Jalle, M Fernandez, J Abella, J Andersson, M Patte, L Fossati, ...
Probabilistic timing analysis on time-randomized platforms for the space domain
M Fernandez, D Morales, L Kosmidis, A Bardizbanyan, I Broster, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
MC2: Multicore and cache analysis via deterministic and probabilistic jitter bounding
E Díaz, M Fernández, L Kosmidis, E Mezzetti, C Hernandez, J Abella, ...
Ada-Europe International Conference on Reliable Software Technologies, 102-118, 2017
Dixie: A retargetable binary instrumentation tool
M Fernández, R Espasa
In Proceedings of the Workshop on Binary Translation, 1999
pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems
M Slijepcevic, M Fernadez, C Hernandez, J Abella, E Quinones, ...
2016 Euromicro Conference on Digital System Design (DSD), 404-412, 2016
Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding
R Espasa, G Sole, M Fernandez
US Patent 9,785,433, 2017
Contention-aware performance monitoring counter support for real-time MPSoCs
J Jalle, M Fernandez, J Abella, J Andersson, P Mathieu, L Fossati, ...
2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), 1-10, 2016
Multicore OS benchmarks
FJ Cazorla, R Gioiosa, M Fernandez, E Quinones
Technical report, European Space Agency, 2012
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems
D Trilla, J Jalle, M Fernandez, J Abella, FJ Cazorla
22nd IEEE Real-Time Embedded Technology & Applications Symposium (RTAS 2016), 2016
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application
E Mezzetti, M Fernandez, A Bardizbanyan, I Agirre, J Abella, T Vardanega, ...
2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2017
Load redundancy elimination on executable code
M Fernández, R Espasa, S Debray
European Conference on Parallel Processing, 221-229, 2001
Link-time path-sensitive memory redundancy elimination
M Fernández, R Espasa
10th International Symposium on High Performance Computer Architecture (HPCA …, 2004
Super multiply add (super madd) instruction
J Corbal, AT Forsyth, R Espasa, M Fernandez, TD Fletcher
US Patent 9,733,935, 2017
Dixie architecture reference manual (version 1.0)
M Fernandez, R Espasa
Technical report, Computer Architecture Department, Universitat Politecnica …, 1998
Apparatus and method for fused add-add instructions
E Ould-Ahmed-Vall, R Valentine, J Corbal, M Charney, R Espasa, G Sole, ...
US Patent App. 14/583,050, 2016
Automatic Generation and Testing of Application Specific Hardware Accelerators on a New Reconfigurable OpenSPARC Platform
C González-Álvarez, M Fernández, D Jiménez-González, C Álvarez, ...
Load redundancy elimination on executable code
M Fernández, R Espasa, S Debray
Concurrency and Computation: Practice and Experience 15 (10), 979-997, 2003
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